We aim to automate decades of research and experience in register allocation, leveraging machine learning. We tackle this problem by embedding a multi-agent reinforcement learning algorithm within LLVM, training it with the state of the art techniques. We formalize the constraints that precisely define the problem for a given instruction-set architecture, while ensuring that the generated code preserves semantic correctness. We also develop a gRPC based framework providing a modular and efficient compiler interface for training and inference. Our approach is architecture independent: we show experimental results targeting Intel x86 and ARM AArch64. Our results match or out-perform the
heavily tuned, production-grade register allocators of LLVM.
Sat 25 FebDisplayed time zone: Eastern Time (US & Canada) change
15:40 - 16:40 | BackendResearch Papers at St. Laurent 3 Chair(s): Yufei Ding University of California at Santa Barbara | ||
15:40 20mTalk | A Symbolic Emulator for Shuffle Synthesis on the NVIDIA PTX Code Research Papers Kazuaki Matsumura Barcelona Supercomputing Center, Simon Garcia de Gonzalo Sandia National Laboratories, Antonio J. Peña Barcelona Supercomputing Center DOI | ||
16:00 20mTalk | Register Allocation for Compressed ISAs in LLVM Research Papers DOI | ||
16:20 20mTalk | RL4ReAl: Reinforcement Learning for Register Allocation Research Papers S. VenkataKeerthy IIT Hyderabad, Siddharth Jain IIT Hyderabad, Anilava Kundu IIT Hyderabad, Rohit Aggarwal IIT Hyderabad, Albert Cohen Google, Ramakrishna Upadrasta IIT Hyderabad DOI |