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LCTES 2017
Wed 21 - Thu 22 June 2017 Barcelona, Spain
co-located with PLDI 2017

Modern embedded processors provide hardware support for cache locking, a mechanism used to facilitate the WCET (Worst-Case Execution Time) calculation of a task. We investigate the problem of integrating task scheduling and cache locking for a set of pre-emptible tasks with individual release times and deadlines on a multicore processor with two level caches. We propose a novel integrated approach that schedules the task set and allocates the locked cache contents of each task to the local caches (L1 caches) and the level two cache (L2 cache). Our approach consists of three major components, the task scheduler, the L1 cache allocator, and the L2 cache allocator. The task scheduler aims at minimizing the number of task preemptions. The L1 cache allocator converts the interference graph of all the tasks scheduled on each core into a DAG by considering the preemptions between tasks and allocates L1 cache space to each task. The L2 cache allocator converts the interference graph of all the tasks into a DAG by using a k-longest-path based graph orientation algorithm and allocates L2 cache space to each task. Both cache allocators significantly improve the utilization of all the caches due to the efficient use of the interference graphs of tasks. We have implemented our approach and compared it with the extended version of the preemption tree-based approach and the static analysis approach without cache locking by using a set of benchmarks from the MRTC benchmark suite and SNU real-time benchmarks. Compared to the extended version of the preemption tree-based approach, the maximum WCRT (Worst Case Response Time) improvement of our approach is 15%. Compared to the static analysis approach, the maximum WCRT improvement of our approach is 37%.

Wed 21 Jun

Displayed time zone: Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna change

15:30 - 17:10
Session 2: Abstraction, Modelling and Scheduling for IoT and Embedded SystemsLCTES 2017 at Vertex WS208
Chair(s): Bernhard Scholz University of Sydney, Australia
15:30
25m
Talk
Optimal Functional Unit Assignment and Voltage Selection for Pipelined MPSoC with Guaranteed Probability on Time Performance
LCTES 2017
Weiwen Jiang Chongqing University, Edwin Sha Chongqing University, Qingfeng Zhuge Chongqing University, China, Hailiang Dong Chongqing University, Xianzhang Chen Chongqing University
15:55
25m
Talk
Integrated IoT Programming with Selective Abstraction
LCTES 2017
Gyeongmin Lee POSTECH, Seonyeong Heo POSTECH, Bongjun Kim POSTECH, Jong Kim POSTECH, Hanjun Kim POSTECH
16:20
25m
Talk
Efficient SMT-based LTL Model Checking of Clock Constraint Specification Language for Real-Time and Embedded Systems
LCTES 2017
Min Zhang East China Normal University, Yunhui Ying
16:45
25m
Talk
Integrating Task Scheduling and Cache Locking for Multicore Real-time Embedded Systems
LCTES 2017
Wenguang Zheng , Hui Wu University of New South Wales, Australia, Chuanyao Nie The University of New South Wales