ICFP/SPLASH 2025
Sun 12 - Sat 18 October 2025 Singapore
Tue 14 Oct 2025 14:45 - 15:10 at Peony SE - MPLR Keynote & Research Paper 2 Chair(s): Tomoharu Ugawa, Tony Hosking

As IoT devices evolve, their microcontroller systems-on-a-chip (SoCs) require higher performance, larger memory, and richer peripherals, resulting in increased power consumption. Integrating low-power (LP) coprocessors into SoCs offers a means to reduce power usage while preserving responsiveness, particularly in sensing tasks. However, LP coprocessors are constrained by limited memory and demand complex, platform-specific handling. These constraints often necessitate application refactoring and careful coordination of inter-processor communication.

We propose a JIT compilation design for managed languages to enhance the efficiency of LP coprocessor usage. These languages tend to increase code size due to dynamic dispatch and runtime checks. Our key idea is a cooperative approach: the interpreter on the main processor traces the application to compile only type-specialized basic blocks to be executed by the LP coprocessor. By combining trace-based compilation with lazy basic block versioning, the approach minimizes the code footprint and reduces processor interaction.

We implemented a prototype for a subset of the dynamically typed, object-oriented language mruby. The prototype supports runtime type checking even on LP coprocessors. This paper presents its design and implementation, along with evaluations on selected applications using LP coprocessors. We report power consumption and code size measurements obtained on the ESP32-C6.

Tue 14 Oct

Displayed time zone: Perth change

13:40 - 15:25
MPLR Keynote & Research Paper 2MPLR at Peony SE
Chair(s): Tomoharu Ugawa University of Tokyo, Tony Hosking Australian National University
13:40
40m
Keynote
Joy of Meta-Tracing Just-in-Time Compilation: More Than Just a VM GeneratorMPLR Keynote
MPLR
Hidehiko Masuhara Institute of Science Tokyo
File Attached
14:20
25m
Talk
A Control-Flow Graph Approach to Language-Agnostic Debugging for Microcontrollers
MPLR
Carlos Rojas Castillo Vrije Universiteit Brussel, Matteo Marra Nokia Bell Labs, Belgium, Elisa Gonzalez Boix Vrije Universiteit Brussel
DOI Pre-print
14:45
25m
Talk
Co-operative JIT Compilation for Resource-Constrained Low-Power Coprocessors
MPLR
Go Suzuki Institute of Science Tokyo, Takuo Watanabe Institute of Science Tokyo, Sosuke Moriguchi Institute of Science Tokyo
DOI Media Attached
15:10
15m
Talk
SmartSweep: Efficient Space Reclamation in Tiered Managed HeapsWIP Research
MPLR
Iacovos Kolokasis University of Crete and FORTH-ICS, Konstantinos Delis University of Crete and FORTH-ICS, Shoaib Akram Australian National University, Foivos S. Zakkak Red Hat, Polyvios Pratikakis University of Crete, Angelos Bilas University of Crete and FORTH, Greece
DOI File Attached