An Analysis of Call-site Patching Without Strong Hardware Support for Self-Modifying-Code
With micro-services continuously gaining popularity and low-power processors making their way into data centers, efficient execution of managed runtime systems on low-power architectures is also gaining interest. Apart from the inherent performance differences between high and low power processors, porting a managed runtime system to a low-power architecture may result in spuriously introducing additional overheads and design trade-offs. In this work we investigate how the lack of strong hardware support for Self Modifying Code (SMC) in low-power architectures, influences Just-In-Time (JIT) compilation and execution in modern virtual machines. In particular, we examine how low-power architectures, with no or limited hardware support for SMC, impose restrictions on call-site implementations, when the latter need to be patchable by the runtime system. We present four different memory-safe implementations for call-site generation and discuss their advantages and disadvantages in the absence of strong hardware support for SMC. Finally, we evaluate each technique on different workloads using micro-benchmarks and we evaluate the best two techniques on the Dacapo benchmark suite showcasing performance differences up to 15%.
Tue 22 OctDisplayed time zone: Beirut change
11:00 - 12:30 | Compilation and code manipulationMPLR 2019 at Room 1 Chair(s): Shigeru Chiba Graduate School of Information Science and Technology, The University of Tokyo | ||
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12:00 30mTalk | An Analysis of Call-site Patching Without Strong Hardware Support for Self-Modifying-Code MPLR 2019 Tim Hartley The University of Manchester, Foivos S. Zakkak University of Manchester, UK, Christos Kotselidis University of Manchester, UK, Mikel Luján University of Manchester Link to publication DOI Authorizer link |