Tue 16 Jun 2015 10:30 - 10:55 at PLDI Main BLUE (Portland 254-255) - Concurrency II Chair(s): Suresh Jagannathan

Self-timed chip designs are commonly specified in a high-level message-passing language called CHP. This language is closely related to Hoare’s CSP except it admits erroneous behavior due to the necessary limitations of efficient hardware implementations. For example, two processes sending on the same channel at the same time causes glitches and short circuits in the physical chip implementation. If a CHP program maintains certain invariants, such as only one process is sending on any given channel at a time, it can guarantee an error-free execution that behaves much like a CSP program would. In this paper, we present an inferable effect system for ensuring that these invariants hold, drawing from model-checking methodologies while exploiting language-usage patterns and domain-specific specializations to achieve efficiency. This analysis is sound, and is even complete for the common subset of CHP programs without data-sensitive synchronization. We have implemented the analysis and demonstrated that it scales to validate even microprocessors.

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Tue 16 Jun

pldi2015-papers
09:15 - 10:55: Research Papers - Concurrency II at PLDI Main BLUE (Portland 254-255)
Chair(s): Suresh JagannathanPurdue University
pldi2015-papers09:15 - 09:40
Talk
Ofri ZivTel Aviv University, Alex AikenStanford University, Guy Golan-GuetaYahoo Labs, G. RamalingamMicrosoft Research, Mooly SagivTel Aviv University
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pldi2015-papers09:40 - 10:05
Talk
Naling ZhangVirginia Tech, Markus KusanoVirginia Tech, Chao WangVirginia Tech
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pldi2015-papers10:05 - 10:30
Talk
Michael Emmi, Constantin EneaLIAFA, Université Paris Diderot, Jad HamzaLIAFA, Université Paris Diderot
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pldi2015-papers10:30 - 10:55
Talk
Stephen LongfieldCornell University, Brittany NkounkouCornell University, Rajit ManoharCornell University, Ross TateCornell University
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