ICSE 2019 (series) / FormaliSE 2019 (series) /
FormaliSE 2019 Program
This is the FormaliSE 2019 program - see the full program for ICSE 2019 and all affiliated events.
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Mon 27 MayDisplayed time zone: Eastern Time (US & Canada) change
Mon 27 May
Displayed time zone: Eastern Time (US & Canada) change
08:40 - 10:30 | |||
08:40 10mDay opening | Welcome by the Chairs FormaliSE | ||
08:50 25mFull-paper | Epistemic Model Checking of Distributed Commit Protocols with Byzantine faults FormaliSE | ||
09:15 25mFull-paper | Clock Reduction in Timed Automata while Preserving Design Parameters FormaliSE Beyazit Yalcinkaya Middle East Technical University, Ebru Aydin Gol Middle East Technical University | ||
09:40 25mFull-paper | Rigorous Design and Deployment of IoT Applications FormaliSE Ajay Krishna Inria Grenoble, France, Michel Le Pallec Nokia Bell Labs, Radu Mateescu INRIA, Ludovic Noirie Nokia Bell Labs, Gwen Salaün University of Grenoble Alpes | ||
10:05 25mFull-paper | Static Analysis for Worst-Case Battery Utilization FormaliSE | ||
10:30 - 11:00 | |||
10:30 30mCoffee break | Coffee break FormaliSE | ||
11:00 - 12:30 | |||
11:00 65mTalk | Keynote presentation: The Benefits of (having doubts about) Formal Methods FormaliSE Jeffrey Joyce Critical System Labs Inc. | ||
12:05 25mFull-paper | FASTEN: An Open Extensible Framework to Experiment with Formal Specification Approaches - Using Language Engineering to Develop a Multi-Paradigm Specification Environment for NuSMV FormaliSE Daniel Ratiu , Marco Gario Siemens Corporate Technology, Hannes Schoenhaar Siemens Corporate Technology | ||
14:00 - 15:30 | |||
14:00 25mFull-paper | Parallelizable Reachability Analysis Algorithms for Feed-Forward Neural Networks FormaliSE Hoang-Dung Tran Vanderbilt University, Patrick Musau Vanderbilt University, Diego Manzanas Lopez Vanderbilt University, Xiao Dong Yang Vanderbilt University, Luan Nguyen University of Pennsylvania, Weiming Xiang Vanderbilt University, Taylor T Johnson Vanderbilt University | ||
14:25 15mShort-paper | Towards Sampling and Simulation-Based Analysis of Featured Weighted Automata FormaliSE Maxime Cordy SnT, University of Luxembourg, Axel Legay , Sami Lazreg Visteon Electronics and Universite Cote d Azur, Philippe Collet University of Nice | ||
14:40 25mFull-paper | Verifying Channel Communication Correctness for a Multi-Core Cooperatively Scheduled Runtime Using CSP FormaliSE | ||
15:05 25mFull-paper | A Generalized Program Verification Workflow Based on Loop Elimination and SA Form FormaliSE Cláudio Belo Lourenço LRI, Université Paris-Sud & INRIA Saclay, Maria João Frade HASLab/INESC TEC & Universidade do Minho, Portugal, Jorge Sousa Pinto HASLab/INESC TEC & Universidade do Minho, Portugal | ||
16:00 - 18:00 | |||
16:00 25mFull-paper | Modular Synthesis of Verified Verifiers of Computation with STV Algorithms FormaliSE Milad K. Ghale The Australian National University, Dirk Pattinson Australian National University, Michael Norrish Data61 at CSIRO, Australia / Australian National University, Australia | ||
16:25 15mShort-paper | A Vision for Helping Developers Use APIs by Leveraging Temporal Patterns FormaliSE Erick Raelijohn University of Montreal, Michalis Famelis Université de Montréal, Houari Sahraoui Université de Montréal | ||
16:40 25mFull-paper | A Proof-Producing Translator for Verilog Development in HOL FormaliSE Andreas Lööw Chalmers University of Technology, Magnus O. Myreen Chalmers University of Technology, Sweden | ||
17:05 25mFull-paper | On the Formalization of Importance Measures using HOL Theorem Proving FormaliSE Waqar Ahmad Carnegie Mellon University, Shahid Ali Murtza National University of Sciences and Technology, Osman Hasan Concordia University, Canada, Sofiene Tahar Concordia University | ||
17:30 30mDay closing | Discussion/closing FormaliSE | ||