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CC 2017
Sun 5 - Mon 6 February 2017 Austin, Texas, United States
Sun 5 Feb 2017 14:45 - 15:10 at 404 - Compilers

We present a translation from programs expressed in a functional IR into dataflow networks as an intermediate step within a Haskell-to-Hardware compiler. Our networks exploit pipeline parallelism, particularly across multiple tail-recursive calls, via non-strict function evaluation. To handle the long-latency memory operations common to our target applications, we employ a latency-insensitive methodology that ensures arbitrary delays do not change the functionality of the circuit. We present empirical results comparing our networks against their strict counterparts, showing that non-strictness can mitigate small increases in memory latency and improve overall performance by up to 2$\times$.

Sun 5 Feb

CC-2017-papers
13:30 - 15:10: Research Papers - Compilers at 404
CC-2017-papers13:30 - 13:55
Talk
Arjun SureshOhio State University, USA, Erven RohouInria, France, André SeznecInria, France
DOI
CC-2017-papers13:55 - 14:20
Talk
Christian Wimmer, Vojin JovanovicOracle Labs, Erik EcksteinOracle Labs, USA, Thomas WuerthingerOracle Labs
DOI
CC-2017-papers14:20 - 14:45
Talk
Nikita PopovTU Berlin, Germany, Biagio CosenzaTU Berlin, Germany, Ben JuurlinkTU Berlin, Germany, Dmitry StogovZend Technologies, Russia
DOI
CC-2017-papers14:45 - 15:10
Talk
Richard TownsendColumbia University, USA, Martha A. KimColumbia University, Stephen Edwards
DOI