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CC 2017
Sun 5 - Mon 6 February 2017 Austin, Texas, United States
Sun 5 Feb 2017 14:45 - 15:10 at 404 - Compilers

We present a translation from programs expressed in a functional IR into dataflow networks as an intermediate step within a Haskell-to-Hardware compiler. Our networks exploit pipeline parallelism, particularly across multiple tail-recursive calls, via non-strict function evaluation. To handle the long-latency memory operations common to our target applications, we employ a latency-insensitive methodology that ensures arbitrary delays do not change the functionality of the circuit. We present empirical results comparing our networks against their strict counterparts, showing that non-strictness can mitigate small increases in memory latency and improve overall performance by up to 2$\times$.

Sun 5 Feb

Displayed time zone: Saskatchewan, Central America change

13:30 - 15:10
CompilersResearch Papers at 404
13:30
25m
Talk
Compile-Time Function Memoization
Research Papers
Arjun Suresh Ohio State University, USA, Erven Rohou Inria, France, André Seznec Inria, France
DOI
13:55
25m
Talk
One Compiler: Deoptimization to Optimized Code
Research Papers
Christian Wimmer , Vojin Jovanovic Oracle Labs, Erik Eckstein Oracle Labs, USA, Thomas Wuerthinger Oracle Labs
DOI
14:20
25m
Talk
Static Optimization in PHP 7
Research Papers
Nikita Popov TU Berlin, Germany, Biagio Cosenza TU Berlin, Germany, Ben Juurlink TU Berlin, Germany, Dmitry Stogov Zend Technologies, Russia
DOI
14:45
25m
Talk
From Functional Programs to Pipelined Dataflow Circuits
Research Papers
Richard Townsend Columbia University, USA, Martha A. Kim Columbia University, Stephen Edwards
DOI