CC 2017 (series) / Research Papers /
Partially Redundant Fence Elimination for x86, ARM, and Power Processors
We show how partial redundancy elimination (PRE) can be instantiated to perform \emph{provably correct}
fence elimination for multi-threaded programs running on top of the x86, ARM and IBM Power relaxed memory models.
We have implemented our algorithm in the backends of the \texttt{LLVM} compiler infrastructure. The optimisation does not induce an observable overhead at compile-time and can result in up-to 10% speedup on some benchmarks.
Sun 5 FebDisplayed time zone: Saskatchewan, Central America change
Sun 5 Feb
Displayed time zone: Saskatchewan, Central America change
10:30 - 12:10 | |||
10:30 25mTalk | Partially Redundant Fence Elimination for x86, ARM, and Power Processors Research Papers DOI | ||
10:55 25mTalk | Lightweight Data Race Detection for Production Runs Research Papers Swarnendu Biswas University of Texas at Austin, Man Cao Ohio State University, Minjia Zhang Ohio State University, Michael D. Bond Ohio State University, Benjamin P. Wood Wellesley College, USA DOI | ||
11:20 25mTalk | Optimized Two-Level Parallelization for GPU Accelerators using the Polyhedral Model Research Papers Jun Shirako Rice University, USA, Akihiro Hayashi Rice University, USA, Vivek Sarkar Rice University, USA DOI | ||
11:45 25mTalk | Optimization Space Pruning without Regrets Research Papers Ulysse Beaugnon , Antoine Pouille ENS, France, Marc Pouzet , Jacques Pienaar Google, USA, Albert Cohen INRIA DOI | ||