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CC 2017
Sun 5 - Mon 6 February 2017 Austin, Texas, United States
Sun 5 Feb 2017 10:30 - 10:55 at 404 - Concurrency & Parallelism Chair(s): Sebastian Hack

We show how partial redundancy elimination (PRE) can be instantiated to perform \emph{provably correct}
fence elimination for multi-threaded programs running on top of the x86, ARM and IBM Power relaxed memory models.
We have implemented our algorithm in the backends of the \texttt{LLVM} compiler infrastructure. The optimisation does not induce an observable overhead at compile-time and can result in up-to 10% speedup on some benchmarks.

Conference Day
Sun 5 Feb

Displayed time zone: Saskatchewan, Central America change

10:30 - 12:10
Concurrency & ParallelismResearch Papers at 404
Chair(s): Sebastian HackSaarland University
10:30
25m
Talk
Partially Redundant Fence Elimination for x86, ARM, and Power Processors
Research Papers
Robin MorissetENS, France, Francesco Zappa NardelliInria, France
DOI
10:55
25m
Talk
Lightweight Data Race Detection for Production Runs
Research Papers
Swarnendu BiswasUniversity of Texas at Austin, Man CaoOhio State University, Minjia ZhangOhio State University, Michael D. BondOhio State University, Benjamin P. WoodWellesley College, USA
DOI
11:20
25m
Talk
Optimized Two-Level Parallelization for GPU Accelerators using the Polyhedral Model
Research Papers
Jun ShirakoRice University, USA, Akihiro HayashiRice University, USA, Vivek SarkarRice University, USA
DOI
11:45
25m
Talk
Optimization Space Pruning without Regrets
Research Papers
DOI