A set of new Hardware Description Languages (HDLs) are
emerging to ease hardware design. HDL compilation time is
a major bottleneck in the designer’s productivity. Moreover,
as the HDLs are developed independently, the possibility to
share innovations in compilation technology is limited.

We design and implement LiveHD, a new multi-threaded,
fast, and generic compilation framework across many HDLs
(FIRRTL, Verilog, and Pyrope). We propose new parallel full
and bottom-up passes to handle HDLs. The resulting compiler
can parallelize all the compiler steps.

LiveHD can achieve 5.5x scalability speedup when elaborating
a CHISEL RISC-V Manycore. It also gets from 7.7x to 8.4x
scalability speedup for a benchmark designed in all three HDLs.
This is achieved with a fast single-threaded LiveHD baseline
with 6x speedup compared to compilers such as Scala-FIRRTL and
8.6x against Yosys on Verilog.