ATVA 2025
Mon 27 - Fri 31 October 2025 Bengaluru, India
Tue 28 Oct 2025 15:00 - 15:30 at R102 - Verification I Chair(s): Kartik Nagar

Upgradation of Programmable Logic Controller (PLC) software is quite common to accommodate evolving industrial requirements. Verifying the correctness of such upgrades remains a significant challenge. In this paper, we propose a verification-based approach to ensure the correctness of the existing functionality in the upgraded version of a PLC software. The method converts the older and the newer versions of the sequential function chart (SFC) into two Petri net models. We then verify whether one model is contained within another, based on a novel containment checking algorithm grounded in symbolic path equivalence. For this purpose, we have developed a home-grown Petri net-based containment checker. Experimental evaluation on 80 real-world benchmarks from the OSCAT library highlights the scalability and effectiveness of the framework. We have compared our approach with verifAPS, a popular tool used for software upgradation, and observed nearly 4x performance improvement.

Tue 28 Oct

Displayed time zone: Chennai, Kolkata, Mumbai, New Delhi change

14:00 - 15:30
Verification IATVA Papers at R102
Chair(s): Kartik Nagar IIT Madras
14:00
30m
Paper
Data Structures for Finite Downsets of Natural Vectors: Theory and Practice
ATVA Papers
Michaƫl Cadilhac , Vanessa Fluegel University of Antwerp, Antwerp, Belgium, Guillermo A. Perez University of Antwerp, Shrisha Rao University of Antwerp, Antwerp, Belgium
14:30
30m
Paper
Generalized Parameter Lifting: Finer Abstractions for Parametric Markov Chains
ATVA Papers
Linus Heck Radboud University, Tim Quatmann RWTH Aachen University, Jip Spel RWTH Aachen University, Joost-Pieter Katoen RWTH Aachen University, Sebastian Junges Radboud University
15:00
30m
Paper
Antarbhukti: Verifying Correctness of PLC Software during System Evolution
ATVA Papers
Soumyadip Bandyopadhyay ACM Member, Santonu Sarkar BITS Pilani, India
Pre-print
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