Name:Augusto Mafra

Bio:

Augusto Mafra is a Lead Software Engineer at Cadence Design Systems Brazil since 2016, working on the HDL Compiler for Jasper Formal Verification Platform, Cadence’s smart formal verification software developed for Hardware C/C++ and RTL level verification. He received a B.S. in Electrical Engineering from UFMG (Minas Gerais, Brazil) in 2018 and is currently pursuing his MSc in Computer Science, also in UFMG.

His main interests are C++ development, SystemVerilog compilers and Hardware Formal Verification. His recent work focuses on debuggers for HDL and research on Formal Verification of Analog and Digital Mixed-Signal Hardware.

Country:Brazil

Affiliation:Cadence Design Systems

Research interests:C++, Formal Verification, Compiler Development, SystemVerilog, Hardware Verification