Brijesh Dongol -

Registered user since Fri 6 Mar 2015

Name:Brijesh Dongol

Country:United Kingdom

Affiliation:University of Surrey

Contributions

2024

SPLASH

Author of Semantics of Remote Direct Memory Access: Operational and Declarative Models of RDMA on TSO Architectures within the OOPSLA 2024-track

Formal Methods for Incorrectness

Author of A Reachability Logic for a Weak Memory Model with Promises within the Incorrectness-track

VMCAI

Author of A Fully Verified Persistency Library within the VMCAI 2024-track

The Future of Weak Memory

2022

FTSCS

Author of Proving Memory Access Violations in Isabelle/HOL within the Formal Techniques for Safety-Critical Systems-track

SPLASH

Author of Implementing and Verifying Release-Acquire Transactional Memory in C11 within the OOPSLA-track

2021

Principles and Practice of Parallel Programming

Author of POSTER: Verifying C11-Style Weak Memory Libraries within the Main Conference-track

CPP

Committee Member in Program Committee within the CPP 2021-track

2020

SPLASH

Author of Owicki-Gries Reasoning for C11 RAR within the Posters-track

ECOOP

2019

FTfJP

Author of Towards Deductive Verification of C11 Programs with Event-B and ProB within the FTfJP 2019-track

Principles and Practice of Parallel Programming

2018

POPL

Author of Transactions in Relaxed Memory Architectures within the Research Papers-track

VMCAI

Author of On abstraction and compositionality for weak-memory linearisability within the VMCAI 2018-track

2015

ECOOP

Author of Defining Correctness Conditions for Concurrent Objects in Multicore Architectures within the Research Track-track