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conf.researchr.org / Andreas Lööw
  • ICSE 2019 profile
  • PLDI 2019 profile
  • POPL 2021 profile

Registered user since Tue 25 Jun 2019

Name:Andreas Lööw
Affiliation:Chalmers University of Technology

Contributions

CPP 2021 Author of Lutsig: A Verified Verilog Compiler for Verified Circuit Development within the CPP 2021-track
FormaliSE 2019 Author of A Proof-Producing Translator for Verilog Development in HOL within the FormaliSE 2019-track
PLDI 2019 Author of Verified Compilation on a Verified Processor within the PLDI Research Papers-track

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