Andreas Lööw -

Registered user since Tue 25 Jun 2019

Name:Andreas Lööw

Country:United Kingdom

Affiliation:Royal Holloway, University of London

Personal website: https://www.cs.rhul.ac.uk/home/upac096/

Contributions

2026

ECOOP

PC Member in Programme Committee within the Technical Papers-track

2025

SPLASH

Author of The Simulation Semantics of Synthesisable Verilog within the OOPSLA-track
Author of Compositional Symbolic Execution for the Next 700 Memory Models within the OOPSLA-track

TPSA

Author of Data Structure Abstraction and Incorrectness Separation Logic within the TPSA 2025-track

2024

ECOOP

Formal Methods for Incorrectness

Author of Unified Compositional Formal Methods: Exact Separation Logic and the Gillian Platform for Correctness and Incorrectness Reasoning within the Incorrectness-track

2023

ECOOP

Author of Exact Separation Logic within the Research Papers-track

PLARCH

Author of They're the same picture: a software-verification flow adapted for hardware verification within the PLARCH 2023-track

2021

CPP

Author of Lutsig: A Verified Verilog Compiler for Verified Circuit Development within the CPP 2021-track

2019

PLDI

Author of Verified Compilation on a Verified Processor within the PLDI Research Papers-track

FormaliSE

Author of A Proof-Producing Translator for Verilog Development in HOL within the FormaliSE 2019-track