Barry Porter -

Registered user since Mon 25 Nov 2019

Name:Barry Porter

Country:United Kingdom

Affiliation:Lancaster University

Personal website:http://www.barryfp.com

Research interests:Adaptive Systems, Operating Systems, Distributed Systems, Machine Learning

Contributions

ACSOS 2023	PC Chair in Organizing Committee Program Chair in Program Committee within the Main Track-track
ACSOS 2022	Special Event Organizer Ireland/UK in Special Event Committee within the Special Events-track Committee Member in Program Committee within the Main Track-track
SEAMS 2022	Author of Emergent Web Server: An Exemplar to Explore Online Learning in Compositional Self-Adaptive Systems within the SEAMS 2022-track
ACSOS 2021	Workshops and Tutorials Chair in Workshop Chair within the Workshops and Tutorials-track Workshops and Tutorials Chair in Organizing Committee PC Member in Program Committee within the Main Track-track Author of A Programming Language for Sound Self-Adaptive Systems within the Main Track-track
GI 2021	Author of Open Challenges in Genetic Improvement for Emergent Software Systems within the GI 2021-track
SEAMS 2021	Author of The Design Space of Emergent Scheduling for Distributed Execution Frameworks within the SEAMS 2021-track
ACSOS 2020	Doctoral Symposium Chair in Organizing Committee Session Chair of User-centric systems (part of Research Papers) Session Chair of Doctoral School Professional Development Talks (part of Doctoral Symposium) PC Member in Program Committee within the Research Papers-track Session Chair of PhD Symposium Session C (part of Doctoral Symposium) Session Chair of PhD Symposium Session A (part of Doctoral Symposium) Session Chair of PhD Symposium Session B (part of Doctoral Symposium) Author of A Survey of Methodology in Self-Adaptive Systems Research within the Research Papers-track Chair in Doctoral Symposium Committee within the Doctoral Symposium-track Session Chair of PhD Lightning Talks (part of Doctoral Symposium)
LCTES 2020	Author of Performance Optimization on big.LITTLE Architectures: A Memory-latency Aware Approach within the LCTES 2020-track