Brijesh Dongol -

Registered user since Fri 6 Mar 2015

Name:Brijesh Dongol

Country:United Kingdom

Affiliation:University of Surrey

Contributions

FTSCS 2022	Author of Proving Memory Access Violations in Isabelle/HOL within the Formal Techniques for Safety-Critical Systems-track
SPLASH 2022	Author of Implementing and Verifying Release-Acquire Transactional Memory in C11 within the OOPSLA-track
PPoPP 2021	Author of POSTER: Verifying C11-Style Weak Memory Libraries within the Main Conference-track
CPP 2021	Committee Member in Program Committee within the CPP 2021-track
SPLASH 2020	Author of Owicki-Gries Reasoning for C11 RAR within the Posters-track
ECOOP 2020	Author of Owicki-Gries Reasoning for C11 RAR within the Posters-track Author of Owicki-Gries Reasoning for C11 RAR within the Artifacts-track Author of Owicki-Gries Reasoning for C11 RAR within the Research Papers-track
FTfJP 2019	Author of Towards Deductive Verification of C11 Programs with Event-B and ProB within the FTfJP 2019-track
PPoPP 2019	Author of Verifying C11 Programs Operationally within the Main Conference-track Author of Modular Transactions: Bounding Mixed Races in Space and Time within the Main Conference-track
POPL 2018	Author of Transactions in Relaxed Memory Architectures within the Research Papers-track
VMCAI 2018	Author of On abstraction and compositionality for weak-memory linearisability within the VMCAI 2018-track
ECOOP 2015	Author of Defining Correctness Conditions for Concurrent Objects in Multicore Architectures within the Research Track-track