Christopher Pulte -

Registered user since Thu 5 Nov 2015

Name: Christopher Pulte

Affiliation: University of Cambridge, UK

Contributions

REMS-DeepSpec 2020	Author of WebAssembly: sequential and concurrent semantics within the REMS-DeepSpec 2020-track Author of Sail: ISA semantics, symbolic execution, and axiomatic concurrency for ARMv8-A and RISC-V within the REMS-DeepSpec 2020-track Presenter of ARMv8 and RISC-V relaxed memory concurrency within the REMS-DeepSpec 2020-track
PLDI 2020	Author of Repairing and Mechanising the JavaScript Relaxed Memory Model within the PLDI Research Papers-track
PLDI 2019	Author of Promising-ARM/RISC-V: A Simpler and Faster Operational Concurrency Model within the PLDI Research Papers-track
POPL 2019	Committee Member in Artifact Evaluation Committee within the Artifact Evaluation-track Author of ISA Semantics for ARMv8-A, RISC-V, and CHERI-MIPS within the Research Papers-track
POPL 2018	Author of Simplifying ARM Concurrency: Multicopy-Atomic Axiomatic and Operational Models for ARMv8 within the Research Papers-track Author of Simplifying ARM Concurrency: Multicopy-atomic Axiomatic and Operational Models for ARMv8 within the Artifact Evaluation-track
POPL 2017	Author of Mixed-size Concurrency: ARM, POWER, C/C++11, and SC within the POPL-track
POPL 2016	Author of Modelling the ARMv8 Architecture, Operationally: Concurrency and ISA within the Research Papers-track