James Riely -

Registered user since Wed 1 Nov 2017

Name:James Riely

Country:United States

Affiliation:DePaul University

Personal website: https://fpl.cs.depaul.edu/jriely/

Contributions

2024

POPL

Committee Member in Program Committee within the POPL-track

2022

POPL

Author of The Leaky Semicolon: Compositional Semantic Dependencies for Relaxed-Memory Concurrency within the POPL-track
Session Chair of Separation Logic (part of POPL)

2021

SPLASH

Author of Pomsets with Preconditions: A Simple Model of Relaxed Memory within the SIGPLAN Papers-track
Session Chair of SLE and DLS 2020 (part of SIGPLAN Papers)

2020

SPLASH

Author of Pomsets with Preconditions: A Simple Model of Relaxed Memory within the OOPSLA-track

2019

Principles and Practice of Parallel Programming

Author of Modular Transactions: Bounding Mixed Races in Space and Time within the Main Conference-track

2018

POPL

Author of Transactions in Relaxed Memory Architectures within the Research Papers-track

VMCAI