Josep Torrellas -

Not registered as user

Name:Josep Torrellas

Affiliation:University of Illinois at Urbana-Champaign

Contributions

2026

HPCA

Author of AccelFlow: Orchestrating an On-Package Ensemble of Fine-Grained Accelerators for Microservices within the Main Conference-track
Author of PhasedStore: Supporting High-performance Write-through Cache-coherence Protocols under TSO within the Main Conference-track
Committee Member in Program Committee

CGO

Author of GRANII: Selection and Ordering of Primitives in GRAph Neural Networks using Input Inspection within the Main Conference-track

2023

Principles and Practice of Parallel Programming

Author of WISE: Predicting the Performance of Sparse Matrix Vector Multiplication with Machine Learning within the Main Conference-track

2019

PLDI

VEE

Author of QuickCheck: Using Speculation to Reduce the Overhead of Checks in NVM Frameworks within the Research Papers-track

2018

SPLASH