Registered user since Wed 27 Jan 2016
Name: José R. Herrero
Bio: J.R. Herrero holds a position as associate professor in the Computer Architecture Department at UPC, BarcelonaTech. Graduated in Computer Science (FIB 1993), Cambridge Proficiency in English (UC, 1994), Postgraduate in Training of University Professors (ICE 1997) and PhD in Computer Science (DAC, UPC 2006).
He has been teaching in the Barcelona School of Informatics (FIB) since 1994. He has taught thirteen different courses corresponding to three different areas (Computer Architecture, Operating Systems, and Parallel Programming), from first-year mandatory subjects to advanced master-level subjects. He has also taught courses at the UPC school in Vilanova i la Geltrú in 1993/94. He has also taught courses abroad at the University of Reading, in UK (2007), ESI-UPB in Burkina Faso (2015), and École Centrale de Marseille, in France (2015). He has tutored students through programs such as ProFEDI, InterCampus, and HPC-Europe and has directed more than thirty final projects or master thesis. He is coauthor of multiple teaching publications and has participated in several teaching innovation projects and the making of two curricula for the FIB. J.R. Herrero has received the Teaching Activity Certification from AQU (2007) and teaching mentions for outstanding quality for five-year periods (UPC 2009 and 2014). He has provided counseling in curriculum making at the National University of Engineering (UNI), Nicaragua, in 1996. He has participated in the working team “Parallel Computing (Supercomputing) Education in Europe: State-of-Art” of Informatics Europe in 2012. He has collaborated with Barcelona Supercomputing Center (BSC) developping a MOOC on Parallel Programming; and with inlab FIB, an innovation and research lab based in the Barcelona School of Informatics, where he lead the Telefónica I+D’s uLab at UPC, and acts as Academic Director of Security and ICT Infrastructures within the Talent training program. He is also member of the inLab’s Talent Program Advisory Board.
He has carried out the duties of Vice-Dean Head of Academic Studies in the Barcelona School of Informatics (FIB), (06/2010-06/2013), coordinating the implementation of the Degree in Informatics Engineering. Later, he acted as Vice-dean for Institutional and International Relations (06/2013-03/2015), also at Barcelona School of Informatics (FIB).
He has combined these management and teaching tasks with research in the field of High Performance Computing, and is a participating member of the group named in the same way. This research work is made tangible in dozens of articles published in scientific magazines and international conferences. He has done research stays in several research centers (UCI, USA; IST, Portugal; NTUA, Greece; BSC, Spain; QUB, UK; ECM, France; UJI, Spain). He regularly takes part in program committees and acts as associate editor and reviewer for scientific publications.
Affiliation: Computer Architecture Department (DAC), UPC, BarcelonaTech
Personal website: http://personals.ac.upc.edu/josepr/
Research interests: High Performance Computing, Energy Efficiency, Fault Tolerance, Approximate Computing, Deep Learning
|PP4REE 2016||Author of On the Energy Costs of Fault Tolerance for Matrix Multiplication on Low-Power Multicore Architectures within the PP4REE 2016-track|