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Weilin Luo
conf.researchr.org general profile
ASE 2022 profile
ASE 2023 profile
ICSE 2021 profile
ICSE 2024 profile
ISSTA/ECOOP 2024 profile
Registered user since Sun 11 Aug 2019
Name:
Weilin Luo
Contributions
2024
ISSTA
Author of Learning to Check LTL Satisfiability and to Generate Traces via Differentiable Trace Checking within the Technical Papers-track
ICSE
Author of ITG: Trace Generation via Iterative Interaction between LLM Query and Trace Checking within the New Ideas and Emerging Results-track
2023
ASE
Author of PURLTL: Mining LTL Specification from Imperfect Traces in Testing within the NIER Track-track
Author of SAT-verifiable LTL Satisfiability Checking via Graph Representation Learning within the NIER Track-track
2022
ASE
Author of Checking LTL Satisfiability via End-to-end Learning within the Research Papers-track
2021
ICSE
Author of How to identify Boundary Conditions with Contrasty Metric? within the Technical Track-track
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