Rafael Asenjo

Registered user since Sat 21 Feb 2015

Name: Rafael Asenjo

Bio: Rafael Asenjo obtained a PhD in Telecommunication Engineering from the U. of Malaga, Spain in 1997. From 2001 to 2017, he was an Associate Professor in the Computer Architecture Department, being a Full Professor since 2017. He collaborated on the IBM XL-UPC compiler and on the Cray’s Chapel runtime. In the last five years, he has focused on productively exploiting heterogeneous chips. In 2013 and 2014 he visited UIUC to work on CPU+GPU chips. In 2015 and 2016 he also started to work on CPU+FPGA chips while visiting U. of Bristol. He has served as General Chair for ACM PPoPP’16 and as an Organization Committee member as well as a Program Committee member for several HPC related conferences (PACT’17, EuroPar’17, SC’15). His research interests include heterogeneous programming models and architectures, parallelization of irregular codes and energy consumption.

Country: Spain

Affiliation: Universidad de Málaga

Personal website: http://www.ac.uma.es/~asenjo

Research interests: Parallel Programming Models, Heterogeneous architectures, Scheduling.

Contributions

PPoPP 2020Steering Committee Member in Steering Committee
CHIUW 2019Committee Member in Program Committee within the CHIUW 2019-track
PPoPP 2019Committee Member in Steering Committee
PPoPP 2018Committee Member in Steering Committee
Author of An Introduction to Intel® Threading Building Blocks (Intel® TBB) and its Support for Heterogeneous Programming within the Tutorials-track
PPoPP 2017Committee Member in Steering Committee
PPoPP 2016General Chair in Organizing Committee
CHIUW 2015Programme Committee in Program Committee within the CHIUW-track