Sylvain Hallé

Registered user since Fri 9 Jun 2017

Name:Sylvain Hallé

I am currently the Canada Research Chair in Software Specification, Testing and Verification at Université du Québec à Chicoutimi, Canada, and head of the Formal Computer Science Laboratory (LIF). My research concentrates on automated verification. Current projects include the runtime monitoring of video games, the detection of configuration errors in network devices and the enforcement of navigation sequences in web applications. I also do a bit of databases and computer security. I applied my knowledge in development or consulting projects with Ericsson Canada, Hydro-Québec, Solutions TLM, BlooBuzz, Novum Solutions and Cisco Systems. Among recent distinctions I received, I earned seven Best Paper Awards in international conferences. I am a double recipient of the Governor General’s Academic Medal. I am also a Senior Member of both IEEE and ACM.

Affiliation:Université du Québec à Chicoutimi
Research interests:Software Testing, Formal Methods, Runtime Verification, Event Stream Processing


ISSTA 2023 PC Member in Technical Papers within the Technical Papers-track
ISSTA 2022 Programme Committee in Program Committee within the Technical Papers-track
ICSE 2022 Committee Member in Program Committee within the Technical Track-track
Author of Synthia: a Generic and Flexible Data Structure Generator within the DEMO - Demonstrations-track
FormaliSE 2022 Author of Test Suite Generation for Boolean Conditions with Equivalence Class Partitioning within the FormaliSE 2022-track
FormaliSE 2021 Author of Runtime Verification Under Access Restrictions within the FormaliSE 2021-track
A-MOST 2021 Author of Test Sequence Generation with Cayley Graphs within the A-MOST 2021-track
ICSE 2019 Session Chair of Specifications and Models (part of Papers)
Committee Member in Program Committee within the Technical Track-track
ISSTA 2017 Author of LabPal: Repeatable Computer Experiments Made Easy within the Demonstrations-track
Author of SealTest: A Simple Library for Test Sequence Generation within the Demonstrations-track