Registered user since Mon 25 May 2020
I am a Senior Staff Software Engineer and Tech Lead at Google, focusing on hardware/software performance, resource efficiency, and co-design for Google’s datacenter fleet and distributed systems infrastructure. Specializing in cross-stack optimization, my work bridges distributed systems and silicon microarchitecture to untangle complex system behaviors, optimize foundational infrastructure, and guide future SoC designs.
Prior to joining Google, I was a postdoctoral researcher at Seoul National University. I received my Master’s and Ph.D. in Electrical Engineering from Princeton University under the supervision of Professor Margaret Martonosi, and a B.S.E. degree from Duke University. My research centers on hardware-software co-design for emerging applications and data access optimizations across systems and architectures.
Throughout my career, I have published 30+ works in top computer architecture and systems venues (ISCA, ASPLOS, MICRO, HPCA, ATC, MLSys, etc.). My research emphasizes architectural acceleration and co-design, with key highly-cited contributions including early Transformer/Attention accelerators and a graph analytics accelerator. My work has been recognized with the Best Paper Award at MICRO-49, IEEE Micro Top Picks (including Honorable Mention), a Best Paper Award Nomination at ISPASS, and the Samsung Scholarship. I also actively serve on program committees for leading conferences in the field.
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