Zhen Yan -

Registered user since Wed 10 Jan 2024

Name:Zhen Yan

Country:China

Affiliation:Tsinghua University

Contributions

2026

SPLASH

Author of VeriEQ: Finding Verilog Simulators and Synthesizers Bugs with Equivalence Circuit Transformation within the OOPSLA-track

ESEC/FSE

Author of Eidolon: Perform Noise-Aware Fuzzing on FHE Libraries via Equivalence Expression Transformation within the Research Papers-track

2025

ICSE

Author of Chord: Towards a Unified Detection of Blockchain Transaction Parallelism Bugs within the Research Track-track

2024

ICSE

Author of Stop Pulling my Rug: Exposing Rug Pull Risks in Crypto Token to Investors within the Software Engineering in Practice-track