Giacomo Valente

Registered user since Wed 29 Oct 2025

Name:Giacomo Valente
Bio:

Giacomo Valente received the M.S. degree in Electronic Engineering in 2014 and the Ph.D. degree in Information and Communication Technology in 2018 from the University of L’Aquila, Italy.

His primary research activities are in electronic design automation, reconfigurable computer architectures, and real-time systems. Since 2022, he has been an Assistant Professor in Computer Architecture at the Department of Information Engineering, Computer Science, and Mathematics (DISIM) of the University of L’Aquila.

He is the author or co-author of about 50 research articles in peer-reviewed journals and international conference proceedings. He has also served as a reviewer and as a member of the Technical Program Committees of several conferences related to his research topics. He is an active member of the DEWS Center of Excellence and of the HiPEAC European network.

Country:Italy
Affiliation:DISIM, University of L'Aquila
Research interests:Real-Time processing, Reconfigurable architectures, Dependable Systems

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