conf.researchr.org / Yung-Hsiang Lu
Registered user since Wed 18 Jan 2023
Name:Yung-Hsiang Lu
Bio:
Yung-Hsiang Lu is a professor of Electrical and Computer Engineering at Purdue University. He is a University Faculty Scholar of Purdue University. He is a fellow of the IEEE (Institute of Electrical and Electronics Engineers), distinguished scientist and distinguished speaker of the ACM (Association for Computing Machinery).
Country:United States
Affiliation:Purdue University
Personal website: https://www.linkedin.com/in/yung-hsiang-lu-51842b22/
Research interests:computer vision, embedded systems
Contributions
2023
ICSE
- Author of Artifact for Technical Track Paper: An Empirical Study of Pre-Trained Model Reuse in the Hugging Face Deep Learning Model Registry within the Artifact Evaluation-track
- Author of An Empirical Study of Pre-Trained Model Reuse in the Hugging Face Deep Learning Model Registry within the Technical Track-track