mPart: Miss-Ratio Curve Guided Partitioning in Key-Value Stores
Web applications employ key-value stores to cache the data that is most commonly accessed.
The cache improves an web application's performance by serving its requests from memory, avoiding
fetching them from the backend database. Since the memory space is limited, maximizing the
memory utilization is a key to delivering the best performance possible. This has lead to
the use of multi-tenant systems, allowing applications to share cache space. In addition, application
data access patterns change over time, so the system should be adaptive in its memory allocation.
In this work, we address both multi-tenancy (where a single cache is used for multiple applications)
and dynamic workloads (changing access patterns) using a model that relates the cache size to the
application miss ratio, known as a miss ratio curve. Intuitively, the larger the cache, the less likely the
system will need to fetch the data from the database.
Our efficient, online construction of the miss ratio curve allows us
to determine a near optimal memory allocation given the available system memory, while
adapting to changing data access patterns.
We show that our model outperforms an existing
state-of-the-art sharing model, Memshare, in terms of overall cache hit ratio
and does so at a lower time cost.
We show that for a typical system, overall hit ratio is consistently 1 percentage point greater and
99.9th percentile latency is reduced by as much as 2.9% under standard web application
workloads containing millions of requests.
Mon 18 JunDisplayed time zone: Eastern Time (US & Canada) change
16:00 - 17:30 | Analyzing the Cache and SchedulingISMM 2018 at Discovery AB Chair(s): Michael D. Bond Ohio State University | ||
16:00 30mTalk | mPart: Miss-Ratio Curve Guided Partitioning in Key-Value Stores ISMM 2018 Daniel Byrne Michigan Technological University, USA, Nilufer Onder Michigan Technological University, USA, Zhenlin Wang Michigan Technological University | ||
16:30 30mTalk | Prediction and Bounds on Shared Cache Demand from Memory Access Interleaving ISMM 2018 Jacob Brock University of Rochester, Chen Ding University of Rochester, Rahman Lavaee , Fangzhou Liu , Liang Yuan Institute of Computing Technology at Chinese Academy of Sciences, China | ||
17:00 30mTalk | Balanced Double Queues for GC Work-Stealing on Weak Memory Models ISMM 2018 Michihiro Horie IBM Research - Tokyo, Hiroshi Horii IBM Research, Japan, Kazunori Ogata IBM Research, Japan, Tamiya Onodera IBM, Japan |