Compiler-Assisted Crash Consistency for PMEMRecorded
Writing crash-consistent programs for memory-semantic storage such as persistent memory (PMEM) is error-prone and cumbersome. Programmers must implement both the main logic and the recovery logic to ensure data consistency after unexpected power failures. Prior work has reduced this burden using compiler-assisted logging techniques to enforce crash consistency. However, these techniques often apply persistence uniformly, limiting support for diverse programming models and incurring high logging overhead.
We present \textbf{SSAPP (Statically and Systematically Automated Persistence is Possible)}, a compiler extension that transparently adds crash consistency to the main logic and automatically generates tailored recovery code. SSAPP persists transient state with low overhead during main logic execution and makes principled resumption decisions during post-failure recovery. Based on these decisions, the generated recovery code correctly completes the interrupted operation. This design supports a broader range of programming models — including lock-free data structures — while reducing crash consistency overhead.
We evaluate SSAPP on transactional benchmarks, lock-based, and lock-free data structures. With minimal developer effort, SSAPP converts volatile lock-free data structures into crash-consistent ones, achieving performance comparable to Mirror, a hand-optimized persistent data structure library. SSAPP also outperforms Clobber-NVM, a prior compiler-based PMEM system, achieving 1.8$\times$ higher throughput.
Tue 17 JunDisplayed time zone: Seoul change
15:40 - 17:05 | Session 4: 1540-1705 [Systems and Architecture]ISMM 2025 at Lilac Chair(s): Steve Blackburn Google and Australian National University | ||
15:40 20mTalk | Fully Randomized Pointers ISMM 2025 Sai Dhawal Phaye National University of Singapore, Gregory J. Duck National University of Singapore, Roland H. C. Yap National University of Singapore, Trevor E. Carlson National University of Singapore DOI | ||
16:00 20mTalk | TierTrain: Proactive Memory Tiering for CPU-Based DNN Training ISMM 2025 Sathvik Swaminathan Intel Labs, Sandeep Kumar Intel Labs, Aravinda Prasad Intel Labs, Sreenivas Subramoney Intel Labs DOI | ||
16:20 20mTalk | EMD: Fair and Efficient Dynamic Memory De-bloating of Transparent Huge PagesRecorded ISMM 2025 Parth Gangar Fujitsu Research of India, Ashish Panwar Microsoft Research India, K. Gopinath Rishihood University DOI | ||
16:40 20mTalk | Compiler-Assisted Crash Consistency for PMEMRecorded ISMM 2025 Yun Joon Soh University of California San Diego, Sihang Liu University of Waterloo, Steven Swanson University of California San Diego, Jishen Zhao University of California San Diego DOI | ||
17:00 5mDay closing | Closing remarks ISMM 2025 |