If much work has been proposed for precise model semantics in the last years, analyzing the root cause of requirements violation in execution traces is still an open issue especially for complex hardware/software system-level designs. A typical example lies in the identification of the reasons for a timing constraint violation (e.g. deadline violation): is it due to an unfavorable real-time scheduling, to contentions on buses, to the characteristics of functional algorithms or hardware components? This understanding is particularly at stake when adding new features in a model, e.g. a new security countermeasure. To address this issue, the paper introduces a new trace analysis technique which objective is to classify execution transactions between two events of interest. To do so, we rely first on a model transformation that builds up a dependency graph from an allocation model, thus including hardware and software aspects of a system model. Then, from this graph and an execution trace, our analysis algorithm can highlight which software or hardware elements of the system model contributed to the delay between the two events. The paper first formalizes the problem and the underlying models before applying our approach to the simulation traces that can be obtained from SysML models. Finally, a case study defined in the scope of the AQUAS H2020 European project illustrates the interest of our approach.