PLARCH 2023 Contributors

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Results (79)

A Rohit AgarwalAgarwal, Rohit University of California, Berkeley New Embedded DSLs for Hardware Design and Verification
Andrew AlexAlex, Andrew UC Santa Barbara On the Generality of Matrix Multiplication
Krste AsanovicAsanovic, Krste University of California Berkeley NFC:Next-generation Formal verification for high performance Caches Nerv: Probabilistic Dynamic Partial Order Reduction for Hardware
Anish AthalyeAthalye, Anish MIT Leakage models are a leaky abstraction: the case for cycle-level verification of constant-time cryptography
B Jonathan BalkindBalkind, Jonathan UC Santa BarbaraUnited States Non-Newtonian Hardware Design for Longevity On the Generality of Matrix Multiplication Semi-Automated Translation of a Formal ISA Specification to Hardware
Clark BarrettBarrett, Clark Stanford UniversityUnited States PEak: A Single Source of Truth for Hardware Design and Verification
Ben BlaxillBlaxill, Ben Groq Silver Oak: Hardware Software Co-Design and Co-Verification in Coq
Thomas BourgeatBourgeat, Thomas MIT CSAIL Hardware Verification of Timing Side Channel Freedom in the Spectre Era
C Vishal CanumallaCanumalla, Vishal University of Washington Generate Compilers from Hardware Models!
Andrew CheungCheung, Andrew University of Washington Generate Compilers from Hardware Models!
Adam ChlipalaChlipala, Adam Massachusetts Institute of TechnologyUnited States Session Chair of PLARCH: Session 1 (part of PLARCH) Hardware Verification of Timing Side Channel Freedom in the Spectre Era Co-chair in Organizing Committee within the PLARCH-track
Samuel CowardCoward, Samuel Imperial College London, UK / Intel CorporationUnited Kingdom Novel Numerical Hardware Design Methodology - From machine readable specification to optimized RTL
D Ross DalyDaly, Ross Stanford University, USA PEak: A Single Source of Truth for Hardware Design and Verification
Caleb DonovickDonovick, Caleb Stanford University PEak: A Single Source of Truth for Hardware Design and Verification
Theo DraneDrane, Theo Intel Corporation, USAUnited States Novel Numerical Hardware Design Methodology - From machine readable specification to optimized RTL
E Kate EseliusEselius, Kate Stanford University Hardware-Software Codesign for Mitigating Spectre
Noah EvansEvans, Noah Sandia National Laboratories Sandia's Formal Hardware Design and Verification, Present and Future
G Prashanth GaneshGanesh, Prashanth University of California, Berkeley Stellar: A DSL to Build and Explore Sparse Accelerators
Dapeng GaoGao, Dapeng University of Cambridge Library-based Compartmentalisation on CHERI
Hasan GencGenc, Hasan UC Berkeley Stellar: A DSL to Build and Explore Sparse Accelerators
Samuel GrütterGrütter, Samuel Massachusetts Institute of Technology Silver Oak: Hardware Software Co-Design and Co-Verification in Coq
H Pat HanrahanHanrahan, Pat Stanford University, USA PEak: A Single Source of Truth for Hardware Design and Verification
Ben HardekopfHardekopf, Ben University of California at Santa BarbaraUnited States Semi-Automated Translation of a Formal ISA Specification to Hardware
Yao HsiaoHsiao, Yao Stanford University Design for Hardware Memory Model Verification
Olivia HsuHsu, Olivia Stanford UniversityUnited States Challenges with Hardware-Software Co-design for Sparse Machine Learning on Streaming Dataflow
I Vighnesh IyerIyer, Vighnesh University of California, Berkeley New Embedded DSLs for Hardware Design and Verification Mixed-Abstraction HDLs and A Discussion on Other Aspects of HDL Design
J René JustJust, René University of WashingtonUnited States Generate Compilers from Hardware Models!
K M. Frans KaashoekKaashoek, M. Frans Massachusetts Institute of Technology, USA Leakage models are a leaky abstraction: the case for cycle-level verification of constant-time cryptography
Hansung KimKim, Hansung University of California, Berkeley Stellar: A DSL to Build and Explore Sparse Accelerators
Fredrik KjolstadKjolstad, Fredrik Stanford UniversityUnited States Challenges with Hardware-Software Co-design for Sparse Machine Learning on Streaming Dataflow
Harlan KringenKringen, Harlan UC Santa Barbara Semi-Automated Translation of a Formal ISA Specification to Hardware
Benjamin KushigianKushigian, Benjamin University of Washington Generate Compilers from Hardware Models!
L Rubens LacoutureLacouture, Rubens Stanford University Challenges with Hardware-Software Co-design for Sparse Machine Learning on Streaming Dataflow
Kevin LaeuferLaeufer, Kevin UC Berkeley New Embedded DSLs for Hardware Design and Verification
Stella LauLau, Stella MIT CSAIL Hardware Verification of Timing Side Channel Freedom in the Spectre Era
Andreas LööwLööw, Andreas Imperial College London They're the same picture: a software-verification flow adapted for hardware verification
M Sharad MalikMalik, Sharad Princeton University Committee Member in Organizing Committee within the PLARCH-track
Jackson MelchertMelchert, Jackson Stanford University PEak: A Single Source of Truth for Hardware Design and Verification
John C. MitchellMitchell, John C. Stanford University Hardware-Software Codesign for Mitigating Spectre
Nicholas MosierMosier, Nicholas Stanford UniversityUnited States Hardware-Software Codesign for Mitigating Spectre
Paul MureMure, Paul Stanford University Tags: A Framework for Distributed Event Ordering
Magnus O. MyreenMyreen, Magnus O. Chalmers University of Technology They're the same picture: a software-verification flow adapted for hardware verification
N Hamed NematiNemati, Hamed Stanford University, CISPA Helmholtz Center for Information Security Hardware-Software Codesign for Mitigating Spectre
Bryan NgoNgo, Bryan University of California, Berkeley New Embedded DSLs for Hardware Design and Verification
Rachit NigamNigam, Rachit Cornell UniversityUnited States Fearless Hardware Design
Borivoje NikolicNikolic, Borivoje University of California, Berkeley New Embedded DSLs for Hardware Design and Verification Mixed-Abstraction HDLs and A Discussion on Other Aspects of HDL Design
O Kunle OlukotunOlukotun, Kunle Stanford UniversityUnited States Tags: A Framework for Distributed Event Ordering Challenges with Hardware-Software Co-design for Sparse Machine Learning on Streaming Dataflow
P Young-Jin ParkPark, Young-Jin University of California, Berkeley New Embedded DSLs for Hardware Design and Verification
Jade PhilipoomPhilipoom, Jade Google, Germany Silver Oak: Hardware Software Co-Design and Co-Verification in Coq
Clément Pit-ClaudelPit-Claudel, Clément EPFLSwitzerland Hardware Verification of Timing Side Channel Freedom in the Spectre Era
R Priyanka RainaRaina, Priyanka Stanford UniversityUnited States PEak: A Single Source of Truth for Hardware Design and Verification
Alastair ReidReid, Alastair Arm LtdUnited Kingdom Goals for a modern ISA specification
S Adrian SampsonSampson, Adrian Cornell University Session Chair of PLARCH: Session 4 (part of PLARCH) Committee Member in Organizing Committee within the PLARCH-track
Koushik SenSen, Koushik University of California at BerkeleyUnited States New Embedded DSLs for Hardware Design and Verification Nerv: Probabilistic Dynamic Partial Order Reduction for Hardware
Yasas SeneviratneSeneviratne, Yasas University of Virginia Design for Hardware Memory Model Verification
Yakun Sophia ShaoShao, Yakun Sophia University of California, Berkeley Stellar: A DSL to Build and Explore Sparse Accelerators
Timothy SherwoodSherwood, Timothy University of California at Santa BarbaraUnited States Semi-Automated Translation of a Formal ISA Specification to Hardware
Jeremy SingerSinger, Jeremy University of GlasgowUnited Kingdom ChatGPT, Make a Secure Malloc for me
Satnam SinghSingh, Satnam GroqUnited States Silver Oak: Hardware Software Co-Design and Co-Verification in Coq
Zachary SiscoSisco, Zachary UC Santa Barbara On the Generality of Matrix Multiplication Semi-Automated Translation of a Formal ISA Specification to Hardware
Kevin SkadronSkadron, Kevin University of Virginia Design for Hardware Memory Model Verification
Gus Henry SmithSmith, Gus Henry University of Washington Generate Compilers from Hardware Models!
T Shangyin TanTan, Shangyin University of California at BerkeleyUnited States Nerv: Probabilistic Dynamic Partial Order Reduction for Hardware
Joseph TassarottiTassarotti, Joseph NYUUnited States Leakage models are a leaky abstraction: the case for cycle-level verification of constant-time cryptography
Zachary TatlockTatlock, Zachary University of WashingtonUnited States Generate Compilers from Hardware Models!
Tommy Tracy IITracy II, Tommy University of Virginia Design for Hardware Memory Model Verification
Caroline TrippelTrippel, Caroline Stanford University Session Chair of PLARCH: Session 3 (part of PLARCH) Hardware-Software Codesign for Mitigating Spectre Design for Hardware Memory Model Verification Tags: A Framework for Distributed Event Ordering Committee Member in Organizing Committee within the PLARCH-track
Leonard TruongTruong, Leonard Stanford University PEak: A Single Source of Truth for Hardware Design and Verification
W Zheng WangWang, Zheng University of Leeds, UK ChatGPT, Make a Secure Malloc for me
Robert N. M. WatsonWatson, Robert N. M. University of Cambridge Library-based Compartmentalisation on CHERI
Tianrui WeiWei, Tianrui University of California, Berkeley NFC:Next-generation Formal verification for high performance Caches Nerv: Probabilistic Dynamic Partial Order Reduction for Hardware
Guy WilksWilks, Guy UC Santa Barbara Non-Newtonian Hardware Design for Longevity
Y Mengjia YanYan, Mengjia MIT Session Chair of PLARCH: Session 2 (part of PLARCH) Co-chair in Organizing Committee within the PLARCH-track
Lixiang YinYin, Lixiang University of California, Berkeley New Embedded DSLs for Hardware Design and Verification
Oliver YuYu, Oliver University of California, Berkeley New Embedded DSLs for Hardware Design and Verification
Z Nickolai ZeldovichZeldovich, Nickolai Massachusetts Institute of Technology, USA Leakage models are a leaky abstraction: the case for cycle-level verification of constant-time cryptography
Nathan ZhangZhang, Nathan Stanford University Tags: A Framework for Distributed Event Ordering
Jerry ZhaoZhao, Jerry UC Berkeley NFC:Next-generation Formal verification for high performance Caches
Bill ZornZorn, Bill Intel Corporation, USA Novel Numerical Hardware Design Methodology - From machine readable specification to optimized RTL