Binoy Ravindran

Registered user since Sat 26 Mar 2022

Name:Binoy Ravindran
Bio:

Binoy Ravindran is a Professor in Virginia Tech’s Department of Electrical and Computer Engineering, where he leads the Systems Software Research Group. His research is broadly in computer systems (e.g., operating systems, concurrency, virtualization, compilers, run-times), with a focus on programmability, performance, security, energy efficiency, and real-time.

Country:United States
Affiliation:Virginia Tech
Research interests:concurrency, distributed systems, operating systems, compilers/run-times, real-time systems

Contributions

PLDI 2022 Author of Formally Verified Lifting of C-compiled x86-64 Binaries within the PLDI-track
PPoPP 2022 Author of POSTER: wCQ: A Fast Wait-Free Queue with Bounded Memory Usage within the Main Conference-track
SPLASH 2021 Author of Snapshot-Free, Transparent, and Robust Memory Reclamation for Lock-Free Data Structures within the SIGPLAN Papers-track
PLDI 2021 Author of Snapshot-Free, Transparent, and Robust Memory Reclamation for Lock-Free Data Structures within the PLDI-track
VEE 2020 Author of Intra-Unikernel Isolation with Intel Memory Protection Keys within the VEE 2020-track
Author of LibrettOS: A Dynamically Adaptable Multiserver-Library OS within the VEE 2020-track
Author of Edge Computing -- the Case for Heterogeneous-ISA Container Migration within the VEE 2020-track
PPoPP 2020 Author of Universal Wait-Free Memory Reclamation within the Main Conference-track
VEE 2019 Author of A Binary-Compatible Unikernel within the Research Papers-track
PPoPP 2019 Author of Scheduling HPC Workloads on Heterogeneous-ISA Architectures within the Posters-track
CPP 2019 Author of Formally Verified Big Step Semantics out of x86-64 Binaries within the CPP 2019-track
VEE 2017 Author of Swift Birth and Quick Death: Enabling Fast Parallel Guest Boot and Destruction in the Xen Hypervisor within the Session 1-track
TRANSACT 2016 Author of On Extending TM Primitives using Low Level Semantics within the TRANSACT 2016-track
Author of Lerna: Transparent and Effective Speculative Loop Parallelization within the TRANSACT 2016-track