BIRD: A Binary Intermediate Representation for formally verified Decompilation of x86-64 binaries
We present BIRD: A Binary Intermediate Representation for formally verified Decompilation of x86-64 binaries. BIRD is a generic language capable of representing a binary program at various stages of decompilation. Decompilation can consist of various small translation passes, each raising the abstraction level from assembly to source code. Where most decompilation frameworks do not guarantee that their translations preserve the program’s operational semantics or even provide any formal semantics, translation passes built on top of BIRD must prove their output to be bisimilar to their input. This work presents the mathematical machinery needed to define BIRD. Moreover, it provides two instantiations — one representing x86-64 assembly, and one where registers have been replaced by variables — as well as a formally proven correct translation pass between them. This translation serves both as a practical first step in trustworthy decompilation as well as a proof of concept that semantic preserving translations of low-level programs are feasible. The entire effort has been formalized in the Coq theorem prover. As such, it does not only provide a mathematical formalism but can also be exported as executable code to be used in a decompiler. We envision BIRD to be used to define provably correct binary-level analyses and program transformations.
Slides (TAP_BIRD.pdf) | 4.94MiB |
Tue 18 JulDisplayed time zone: London change
13:30 - 15:00 | TAP Session 2: Low-level code verificationResearch Papers at Oak Chair(s): Julien Signoles Université Paris-Saclay, CEA, List Remote Participants: Zoom Link | ||
13:30 30mTalk | BIRD: A Binary Intermediate Representation for formally verified Decompilation of x86-64 binaries Research Papers P: Daniel Engel Open University Of The Netherlands, Freek Verbeek Open University of the Netherlands, The Netherlands, Binoy Ravindran Virginia Tech DOI Pre-print File Attached | ||
14:00 30mTalk | Low-level Reachability Analysis based on Formal Logic Research Papers P: Nico Naus Virginia Tech, Freek Verbeek Open University of the Netherlands, The Netherlands, Marc Schoolderman Radboud University Nijmegen, Binoy Ravindran Virginia Tech DOI Pre-print | ||
14:30 30mTalk | Testing a Formally Verified Compiler Research Papers P: David Monniaux CNRS/VERIMAG, Léo Gourdin Université Grenoble Alpes, Verimag, Sylvain Boulmé Grenoble Alps University / CNRS / Grenoble INP / VERIMAG, Olivier Lebeltel Université Grenoble Alpes, CNRS, Verimag DOI Pre-print |