conf.researchr.org / Azalea Raad
Registered user since Wed 7 Jan 2015
Name:Azalea Raad
Country:United Kingdom
Affiliation:Imperial College London
Personal website: https://www.SoundAndComplete.org
Research interests:Weak Memory Concurrency, Non-Volatile Memory, Program Logics, Separation Logic, Concurrent Reasoning, Verification
Contributions
2025
TPSA
- Author of U-turn: Forward-driven backward analysis for incorrectness within the TPSA 2025-track
- Committee Member in Organizing Committee within the TPSA 2025-track
- Committee Member in Program Committee within the TPSA 2025-track
- Author of Scalable Bug Detection for Internally Unsafe Libraries: A Logical Approach to Type Refutation within the TPSA 2025-track
2024
SPLASH
- Author of Semantics of Remote Direct Memory Access: Operational and Declarative Models of RDMA on TSO Architectures within the OOPSLA 2024-track
- Author of Non-Termination Proving at Scale within the OOPSLA 2024-track
- Author of Extending the C/C++ Memory Model with Inline Assembly within the OOPSLA 2024-track
Formal Methods for Incorrectness
- Committee Member in Program Committee within the Incorrectness-track
- Author of Welcome within the Incorrectness-track
- Organizer in Organizing Committee within the Incorrectness-track
- Session Chair of Concurrency, Security, & Hyper-properties (part of Incorrectness)
- Session Chair of Types (part of Incorrectness)
O'Hearn Fest
2023
POPL
- Committee Member in Program Committee within the POPL-track
- Author of Incorrectness Logic and Under-approximation: Foundations of Bug Catching within the TutorialFest-track
- Author of The Path to Durable Linearizability within the POPL-track
- Panelist of Panel: Next 50 Years of POPL within the POPL-track
2022
Infer
POPL
- Author of Student Research Competition Winners within the POPL-track
- Student Research Competition Co-Chair in Organizing Committee
- Co-chair in Selection Committee within the Student Research Competition-track
- Author of Concurrent Incorrectness Separation Logic within the POPL-track
- Author of Extending Intel-x86 Consistency and Persistency: Formalising the Semantics of Intel-x86 Memory Types and Non-temporal Stores within the POPL-track
2021
PLDI
- Committee Member in Program Committee within the PLDI-track
- Author of Beyond Weak Memory Consistency: The Challenges of Memory Persistency within the Tutorials-track
- Author of Revamping Hardware Persistency Models: View-Based and Axiomatic Persistency Models for Intel-x86 and Armv8 within the PLDI-track
POPL
2020
SPLASH
PLDI
POPL
- Committee Member in Program Committee within the Research Papers-track
- Committee Member in Selection Committee within the Student Research Competition-track
- Author of Persistency Semantics of the Intel-x86 Architecture within the Research Papers-track
- Session Chair of Program Logics (part of Research Papers)
2019
SPLASH
- Author of Effective Lock Handling in Stateless Model Checking within the Posters-track
- Author of Effective Lock Handling in Stateless Model Checking within the OOPSLA-track
- Author of Weak Persistency Semantics from the Ground Up: Formalising the Persistency Semantics of ARMv8 and Transactional Models within the OOPSLA-track
- Author of Effective Lock Handling In Stateless Model Checking within the OOPSLA Artifacts-track
- Panelist of Panel: Current PhD Students and Postdocs within the PLMW-track
- Panelist in Speakers & Panelists within the PLMW-track