Memory persistency models provide the foundational rules for software engineers to develop applications that take advantage of non-volatile memory (NVM), dictating which (and when) writes to NVM are deemed persistent. Though formalised for Intel-x86 and Arm architectures, these models remain empirically unvalidated on actual machines. Conventional validation methods for memory \emph{consistency} models fall short as test programs cannot differentiate between volatile cache reads and those from NVM.
To address this, we employed a commercial device to intercept and log data on the memory bus in their order of arrival. Through this, we conducted a campaign using \emph{litmus tests}—small programs designed to assess specific memory persistency behaviours—aimed at empirically validating Intel-x86 and Arm machine persistency guarantees.

We noted out-of-order memory writes and ensured they were not merely artifacts of our test setup. Analysis revealed Intel-x86’s architecture \emph{cannot} be validated via memory bus interception due to legitimate early subsystem reordering. Intel engineers confirmed the absence of dependable validation methods for their persistency claims. Meanwhile, an expert-backed Arm machine didn’t align with the formal persistency model due to a specification lapse, and further investigation suggests that no market-available Arm machine fully supports NVM.

Our negative result for Intel highlights a major concern for software developers wishing to take advantage of NVM: currently there is, to our knowledge, \emph{no viable way} to confirm the persistency guarantees claimed by Intel. Our results for Arm suggest that our interception-based approach is viable for reliably detecting reorderings in the memory subsystem, which will be valuable for empirical validation once NVM-supporting machines become available.