Dejice Jacob -

Registered user since Wed 21 Aug 2019

Name:Dejice Jacob

Country:United Kingdom

Affiliation:University of Glasgow

Personal website: http://www.dcs.gla.ac.uk/~jacobd

Contributions

2025

ISMM

Author of SecureMind: A Framework for Benchmarking Large Language Models in Memory Bug Detection and Repair within the ISMM 2025-track

CC

Author of Secure Scripting with CHERIoT MicroPython within the Main Conference-track

2024

VMIL

2023

VMIL

Author of CHERI Performance Enhancement for a Bytecode Interpreter within the VMIL-track

MPLR

Author of Morello MicroPython: A Python Interpreter for CHERI within the MPLR 2023-track

ISMM

Author of Picking a CHERI Allocator: Security and Performance Considerations within the ISMM 2023-track

2022

VEE

Author of Capability Boehm: Challenges and Opportunities for Garbage Collection with Capability Hardware within the Research Papers-track

2021

DLS

PC Member in Program Committee within the DLS 2021-track

2020

DLS

Author of Pricing Python Parallelism: A Dynamic Language Cost Model for Heterogeneous Platforms within the DLS 2020-track

2019

DLS

Author of Python Programmers have GPUs too: Automatic Python Loop Parallelization with Staged Dependence Analysis within the DLS 2019-track

ARRAY

Author of ALPyNA: Acceleration of Loops in Python for Novel Architectures within the ARRAY 2019-track