Kyungmin Bae -

Registered user since Tue 6 Nov 2018

Name:Kyungmin Bae

Country:South Korea

Affiliation:POSTECH

Personal website:http://sevlab.postech.ac.kr/~kmbae/

Research interests:Model checking, automated reasoning, formal methods

Contributions

FormaliSE 2023	Committee Member in Program Committee within the FormaliSE 2023-track
APSEC 2023	Committee Member in Program Committee within the Technical Track-track
FTSCS 2023	Committee Member in Program Committee within the FTSCS 2023-track
FTSCS 2022	Author of Rewriting Logic Semantics and Symbolic Analysis for Parametric Timed Automata within the Formal Techniques for Safety-Critical Systems-track Committee Member in Program Committee within the Formal Techniques for Safety-Critical Systems-track Author of Symbolic Reachability Analysis of Distributed Systems using Narrowing and Heuristic Search within the Formal Techniques for Safety-Critical Systems-track Author of Bounded Model Checking of PLC ST Programs using Rewriting Modulo SMT within the Formal Techniques for Safety-Critical Systems-track
APSEC 2022	Committee Member in Program Committee within the Technical Track-track
FormaliSE 2022	Committee Member in Program Committee within the FormaliSE 2022-track
ASE 2021	Author of Efficient SMT-Based Model Checking for Signal Temporal Logic within the Research Papers-track Author of Efficient SMT-Based Model Checking for Signal Temporal Logic within the Artifact Evaluation-track
APLAS 2021	Committee Member in Program Committee within the Research Papers-track
FormaliSE 2021	Committee Member in Programme Committee within the FormaliSE 2021-track
ECSA 2020	Committee Member in Program Committee within the Gender Diversity in SA-track
ICSE 2020	Committee Member in Program Committee within the Demonstrations-track Programme Committee in Program Committee within the Software Engineering in Practice-track Publicity Co-Chair in Organizing Committee
FormaliSE 2020	Program Co-Chair in Program Committee within the FormaliSE 2020-track
POPL 2019	Author of Bounded Model Checking of Signal Temporal Logic Properties Using Syntactic Separation within the Research Papers-track