Zehong Yu -

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Name:Zehong Yu

Country:China

Affiliation:Tsinghua University

Contributions

2026

ASE

Committee Member in Artifact Evaluation Committee within the Artifact Evaluation-track
Author of UCT: A Versatile Code Translation Framework Based on a Unified Intermediate Representation within the Tools and Datasets-track

ISSTA

Committee Member in Artifact Evaluation Committee within the Artifact evaluation-track

SPLASH

Author of VeriEQ: Finding Verilog Simulators and Synthesizers Bugs with Equivalence Circuit Transformation within the OOPSLA-track

ICSE

Author of Synthesizing Hardware-Specific Instructions for Efficient Code Generation of Simulink within the Research Track-track

2024

ASE

Author of Test Case Generation for Simulink Models using Model Fuzzing and State Solving within the Research Papers-track