Achieving Yield, Density and Performance Effective DRAM
The impending doom of DRAM in mobile and embedded systems is being predicted by many, with numerous new memory technologies appearing on the horizon as alternatives. Yet, we haven’t reached that horizon, and DRAM remains as the best choice for main memory in most systems. It strikes an ideal balance of cost, performance, capacity and energy. There are, however, significant challenges to scaling DRAM, arising from process variations (PV). PV in the transistor and capacitor of a bit cell, along with other components, can cause critical requirements to be violated, including retention capability, reliability and operational timing. While retention and reliability have received much attention, the challenge of meeting timing requirements has been much less considered. This challenge stands as an equal to the others for continued cost-effective production and deployment of DRAM in mobile and embedded systems.
In this talk, I will argue that timing requirements must be relaxed and exposed on a per-location basis for management by the memory sub-system architecture. This “soft yield” approach trades exposed timing variability for enhanced yield, without harming chip density. Because relaxing and exposing variable timing can lead to application performance loss, a suite of architecture techniques must be applied to mitigate the loss. I will describe two such general techniques: (1) forming and partitioning physical memory rows into logical fast and slow rows, and (2) truncating restore operations to improve performance of DRAM that uses relaxed timing. With these techniques, main memory can be constructed from DRAM devices that violate timing parameters, which would normally be discarded as failed, without unduly harming application performance.
Bruce Childers is a Professor of Computer Science (CS) at the University of Pittsburgh. He graduated from the University of Virginia with a PhD (CS, 2000) and from the College of William and Mary with a BS (CS, 1991). Childers’ research spans the software-hardware boundary for improved energy, performance and reliability, with an emphasis on embedded systems. He has developed techniques at both the software layer (dynamic binary translation, compiler optimization, debugging and software testing) and the hardware layer (asynchronous custom processors, speed scaling, reliable cache design, and storage class memory). Childers is also a passionate believer in increasing accountability in computer systems research for more reproducible and open experimentation.