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LCTES 2017
Wed 21 - Thu 22 June 2017 Barcelona, Spain
co-located with PLDI 2017

In this paper, we present a checkpointing-aware loop tiling method for energy harvesting powered non-volatile processors. As power failures of energy harvesting system happen naturally, checkpointing is needed during the program execution. We observe that checkpointing is implemented with high overhead in applications with loops. We are motivated to reduce the amount of checkpointing data by analyzing data locality and shortening data lifetime in loops. This paper proposes checkpointing-aware loop tiling techniques which target to reduce the checkpointing and recovering overheads for loops. First, we analyze the optimal tile size for the nest loops considering checkpointing distance. Then, checkpointing and recovery schemes for tiling loops are proposed. Finally, the experiments are implemented to evaluate the effectiveness. The experimental results show that compared to the most related work, the proposed method reduce the checkpointing and recovering overheads significantly.