Traditional programming approaches such as CUDA and OpenCL intertwine the definition of the computation (e.g. matrix multiplication) with the optimization of it (e.g.) tiling in a single programming language. This results in significantly reduced portability of such programs because the specific optimizations necessary to achieve high performance on different hardware architectures differs greatly. Recently, new programming approaches such as Halide, TVM and ELEVATE have emerged with attempts to solve this problem. They aim to separate the concerns of expressing an optimized program by dividing it into a program and an optimization schedule. We explore how such an approach can be realized is the SSA-based MLIR compiler infrastructure.