CGO 2024
Sat 2 - Wed 6 March 2024 Edinburgh, United Kingdom
Mon 4 Mar 2024 10:40 - 11:00 at Tinto - Compilers for machine learning Chair(s): Fabrice Rastello

Polyhedral techniques have been widely used for automatic code optimization in low-level compilers and higher-level processes.
Loop optimization is central to this technique, and several polyhedral schedulers like Feautrier, Pluto, isl and Tensor Scheduler have been proposed, each of them targeting a different architecture, parallelism model, or application scenario.
The need for scenario-specific optimization is growing due to the heterogeneity of architectures.
One of the most critical cases is represented by NPUs (Neural Processing Units) used for AI, which may require loop optimization with different objectives.
Another factor to be considered is the framework or compiler in which polyhedral optimization takes place.
Different scenarios, depending on the target architecture, compilation environment, and application domain, may require different kinds of optimization to best exploit the architecture feature set.

We introduce a new configurable polyhedral scheduler, PolyTOPS, that can be adjusted to various scenarios with straightforward, high-level configurations. This scheduler allows the creation of diverse scheduling strategies that can be both scenario-specific (like state-of-the-art schedulers) and kernel-specific, breaking the concept of a one-size-fits-all scheduler approach.
PolyTOPS has been used with isl and CLooG as code generators and has been integrated in MindSpore AKG deep learning compiler. Experimental results in different scenarios show good performance:
a geomean speedup of 7.66x on MindSpore (for the NPU Ascend architecture) hybrid custom operators over isl scheduling,
a geomean speedup up to 1.80x on PolyBench on different multicore architectures over Pluto scheduling. Finally, some comparisons with different state-of-the-art tools are presented in the PolyMage scenario.

Mon 4 Mar

Displayed time zone: London change

10:00 - 11:00
Compilers for machine learningMain Conference at Tinto
Chair(s): Fabrice Rastello University Grenoble Alpes - Inria - CNRS - Grenoble INP - LIG
A Tensor Algebra Compiler for Sparse Differentiation
Main Conference
Amir Shaikhha University of Edinburgh, Mathieu Huot University of Oxford, Shideh Hashemian University of Edinburgh
Energy-Aware Tile Size Selection for Affine Programs on GPUs
Main Conference
Malith Jayaweera Northeastern University, Martin Kong Ohio State University, Yanzhi Wang Northeastern University, David Kaeli Northeastern University
PolyTOPS: Reconfigurable and Flexible Polyhedral Scheduler
Main Conference
Gianpietro Consolaro Huawei Technologies; Mines Paris-PSL, Zhen Zhang Huawei Technologies, Harenome Razanajato Huawei Technologies, Nelson Lossing Huawei Technologies, Nassim Tchoulak Huawei Technologies, Adilla Susungi Huawei Technologies, Artur Cesar Araujo Alves Huawei Technologies, Renwei Zhang Huawei Technologies, Denis Barthou Huawei Technologies, Corinne Ancourt Mines Paris-PSL, Cédric Bastoul Huawei Technologies