This tutorial presents a new end-to-end tensor compiler infrastructure designed to support emerging tensor accelerators.

Recent years have seen a proliferation of specialized ML accelerators - proposed in both academia (e.g., Gemmini, FEATHER) and industry (e.g., Google TPU, Intel AMX) - that depart significantly from traditional CPU/GPU architectures. However, research on compiler and systems support for these accelerators remains sparse, largely due to the lack of open-source compiler infrastructures capable of targeting them from modern ML frameworks like PyTorch, TensorFlow, and JAX. Building such support typically involves considerable manual effort, slowing innovation and creating a gap between hardware and software research communities.

Our infrastructure closes this gap by automatically generating compiler support from a high-level description of an accelerator’s ISA. It enables rapid prototyping and evaluation of architecture-specific optimizations, significantly lowering the gap for systems research on non-traditional architectures.

In this tutorial, we will walk through compiling real-world ML models to various existing accelerators and demonstrate how the infrastructure can be extended to support new designs. The goal is to provide attendees with practical insights and tools to accelerate systems and compiler research in the evolving ML hardware landscape.