Blogs (2) >>
ISMM 2017
Sun 18 Jun 2017 Barcelona, Spain
co-located with PLDI 2017
Sun 18 Jun 2017 14:30 - 15:00 at Aula Master - Session 3: Hybrid Memory Systems Chair(s): Ben L. Titzer

This paper addresses the challenges of coupling byte addressable non-volatile memory (NVM) and hardware transaction memory (HTM) in high-performance transaction processing. We first show that HTM transactions can be ordered using existing processor instructions without any hardware changes. In contrast, existing solutions posit changes to HTM mechanisms in the form of special instructions or modified functionality. We exploit the ordering mechanism to design a novel persistence method that decouples HTM concurrency from back-end NVM operations. Failure atomicity is achieved using redo logging coupled with aliasing to guard against mistimed cache evictions. Our algorithm uses efficient lock-free mechanisms with bounded static memory requirements. We evaluated our approach using both micro-benchmarks, and, benchmarks in the STAMP suite, and showed that it compares well with standard (volatile) HTM transactions. We also showed that it yields significant gains in throughput and latency in comparison with persistent transactional locking.

Sun 18 Jun
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14:00 - 15:30: ISMM 2017 - Session 3: Hybrid Memory Systems at Aula Master
Chair(s): Ben L. TitzerGoogle
ismm-2017-papers14:00 - 14:30
Mohammad DashtiUniversity of British Columbia, Alexandra (Sasha) FedorovaSimon Fraser University
ismm-2017-papers14:30 - 15:00
Ellis GilesRice University, Kshitij DoshiIntel Corporation, Peter VarmanRice University
ismm-2017-papers15:00 - 15:30
Ivy Bo PengKTH Royal Institute of Technology, Roberto GioiosaPacific Northwest National Laboratory, Gokcen KestorPacific Northwest National Laboratory, Stefano MarkidisKTH Royal Institute of Technology, Pietro CicottiSan Diego Supercomputer Center, Erwin LaureKTH Royal Institute of Technology