Wang Yi is professor with a chair in Embedded Systems at Uppsala University.

Wang received his Ph.D. in Computer Science in 1991 from Chalmers University of Technology. He is one of the initial contributors to the research area on verification of timed systems. As a co-founder of UPPAAL, a model checker for concurrent and real-time systems, he received the CAV 2013 Award (with Kim Larsen and Paul Pettersson). His current interests include models, algorithms and software tools for modeling and verification, timing analysis, real-time scheduling, and their application to the design of embedded and real-time as well as mixed-criticality systems. He received the Outstanding paper award of ECRTS 2012 and Best Paper Awards of RTSS 2009, DATE 2013, ECRTS 2015 and RTSS 2015 (with Ekberg, Guan, Stigge), and Best Tool Paper of ETAPS 2002 (with Fersman et al).

Wang has been an editor for several journals including IEEE Transactions on Computers and PC chair for TACAS 2001, FORMATS 2005, EMSOFT 2006, HSCC 2011 and LCTES 2012, SETTA 2015 and track/topic Chair for RTSS 2008 and DATE 2012-2014. He is also serving on the steering committee of FORMATS, EMSOFT (co-chair), LCTES and ESWEEK. He is a fellow of the IEEE and an elected member of Academy of Europe.