Registered user since Thu 30 Jun 2022
Name:Virendra Ashiwal
Bio:
Ph.D. student and researcher at LIT CPS Lab, Johannes Kepler University, Linz (Austria). Currently, working on PLC Service bus concept to improve modularity and adaptability of PLC-Software. Previously he had worked around 4.5 years at B&R Industrial Automation, Eggelsberg (Austria) as a “Technical expert in Process and factory automation”.
Country:Austria
Affiliation:LIT CPS Lab, Johannes Kepler University Linz
Twitter:https://twitter.com/ashiwalv
GitHub:https://github.com/ashiwalv
Research interests:IEC 61499, IEC 61131, PLC software architecture, Industry 4.0, Factory Automation,
Contributions
| ECSA 2022 | Apache Kafka as a Middleware to Support the PLC-Service Bus Architecture with IEC 61499 | ||||||||||||||||||||||||||||||||||||||||
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