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LCTES 2018
co-located with PLDI 2018

Level-one data cache (L1 DC) accesses impact energy usage as they frequently occur and use significantly more energy than register file accesses. A memory access instruction consists of an address generation operation calculating the location where the data item resides in memory and the data access operation that loads/stores a value from/to that location. We propose to decouple these two operations into separate machine instructions to reduce energy usage. By associating the data translation lookaside buffer (DTLB) access and level-one data cache (L1 DC) tag check with an address generation instruction, only a single data array in a set-associative L1 DC needs to be accessed during a load instruction when the result of the tag check is known at that point. In addition, many DTLB accesses and L1 DC tag checks are avoided by memoizing the DTLB way and L1 DC way with the register that holds the memory address to be dereferenced. Finally, we are able to often coalesce an ALU operation with a load or store data access using our technique to reduce the number of instructions executed.

Tue 19 Jun

14:00 - 15:40: LCTES 2018 - Full paper session on Adaptation and Hardware at Discovery AB
LCTES-2018-papers14:00 - 14:25
Ben TaylorLancaster University, UK, Vicent Sanz MarcoLancaster University, Willy WolffLancaster University, Yehia ElkhatibLancaster University, Zheng WangLancaster University
LCTES-2018-papers14:25 - 14:50
Lei Han, Zhaoyan ShenThe Hong Kong Polytechnic University, Zili ShaoThe Hong Kong Polytechnic University, Tao LiUniversity of Florida
LCTES-2018-papers14:50 - 15:15
Bernhard EggerSeoul National University, Eunjin SongSeoul National University, Hochan LeeSeoul National University, Daeyoung ShinSeoul National University
LCTES-2018-papers15:15 - 15:40
Michael StokesFlorida State University, Ryan BairdFlorida State University, Zhaoxiang JinMichigan Technological University, David B. Whalley, Soner OnderMichigan Technological University