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LCTES 2018
co-located with PLDI 2018
Tue 19 Jun 2018 16:25 - 16:40 at Discovery AB - WIP paper session

Deep Neural Networks (DNNs) are the algorithm of choice for image processing applications. DNNs present highly parallel workloads that lead to the emergence of custom hardware accelerators. Deep Learning (DL) models specialized in different tasks require a programmable custom hardware and a compiler/mapper to efficiently translate different DNNs into an efficient dataflow in the accelerator. The goal of this paper is to present a compiler for running DNNs on Snowflake, which is a programmable hardware accelerator that targets DNNs. The compiler correctly generates instructions for various DL models: AlexNet, VGG, ResNet and LightCNN9. Snowflake, with a varying number of processing units, was implemented on FPGA to measure the compiler and Snowflake performance properties upon scaling up. The system achieves 70 frames/s and 4.5 GB/s of off-chip memory bandwidth for AlexNet without linear layers on Xilinx’s Zynq-SoC XC7Z045 FPGA.

Tue 19 Jun
Times are displayed in time zone: (GMT-04:00) Eastern Time (US & Canada) change

16:10 - 17:25: LCTES 2018 - WIP paper session at Discovery AB
LCTES-2018-papers16:25 - 16:40
Andre Xian Ming ChangFWDNXT and Purdue, Aliasger ZaidyFWDNXT and Purdue, Lukasz BurzawaFWDNXT and Purdue, Eugenio CulurcielloFWDNXT and Purdue
LCTES-2018-papers16:40 - 16:55
Bharti ChimdyalwarTata Consultancy Services, Priyanka DarkeTata Consultancy Services
LCTES-2018-papers16:55 - 17:10
Francisco Sant'AnnaRio de Janeiro State University, Alexandre SztajnbergRio de Janeiro State University, Noemi RodriguesPUC-Rio, Ana Lúcia de Moura
LCTES-2018-papers17:10 - 17:25
Pavan MehrotraStanford University, Sabar DasguptaStanford University, Samantha RobertsonStanford University, Paul NuyujukianStanford University
Link to publication DOI Pre-print Media Attached