Write a Blog >>
LCTES 2019
Sat 22 - Fri 28 June 2019 Phoenix, Arizona, United States
co-located with PLDI 2019
Sun 23 Jun 2019 11:50 - 12:05 at 105A - Session 2: Architecture and Compilers Chair(s): Na Meng

Hyper-blocks can significantly improve instruction level parallelism on a wide range of super-scalar and VLIW processors. However, most hyper-block construction approaches aim at minimizing the average-case execution time of a program. In real-time embedded systems, minimizing the worst-case execution time (WCET) of a program is the primary goal of an optimizing compiler. We investigate the hyper-block construction problem for a program executed on a clustered VLIW processor such that the WCET of the program is minimized, and propose a novel heuristic approach considering tail duplications. Our approach is underpinned by a novel priority scheme and a precise tail duplication cost model for computing the WCET of a program. We have implemented our approach in Trimaran 4.0, and compared it with the state-of-the-art approach by using a set of 8 benchmark suites. The experimental results show that our approach achieves the maximum WCET improvement of 20.37% and the average WCET improvement of 11.59%, respectively.

Sun 23 Jun
Times are displayed in time zone: Tijuana, Baja California change

11:20 - 12:35: Session 2: Architecture and CompilersLCTES 2019 at 105A
Chair(s): Na MengVirginia Tech
11:20 - 11:35
Full-paper
From Java to Real-Time Java: A Model-Driven Methodology with Automated Toolchain (Invited)
LCTES 2019
Wanli ChangUniversity of York, Shuai ZhaoUniversity of York, Ran WeiUniversity of York, Andy WellingsUniversity of York, Alan BurnsUniversity of York
11:35 - 11:50
Full-paper
The Betrayal of Constant Power × Time: Finding the Missing Joules of Transiently-Powered Computers
LCTES 2019
Saad AhmedLUMS, Pakistan, Abu BakarNorthwestern University, US, Naveed Anwar BhattiRISE, Sweden, Muhammad Hamad AlizaiLUMS, Pakistan, Junaid Haroon SiddiquiLahore University of Management Sciences, Luca MottolaPolitecnico di Milano, Italy and RI.Se SICS, Sweden
11:50 - 12:05
Full-paper
WCET-Aware Hyper-Block Construction for Clustered VLIW Processors
LCTES 2019
Xuesong SuUNSW Sydney, Hui WuUniversity of New South Wales, Australia, Jingling XueUNSW Sydney
12:05 - 12:20
Full-paper
SPECTRUM: A Software Defined Predictable Many-core Architecture for LTE Baseband Processing
LCTES 2019
Vanchinathan VenkataramaniNational University of Singapore, Aditi KulkarniNational University of Singapore, Tulika MitraNational University of Singapore, Singapore, Li-Shiuan PehNational University of Singapore
12:20 - 12:35
Full-paper
Efficient Intermittent Computing with Differential Checkpointing
LCTES 2019
Saad AhmedLUMS, Pakistan, Naveed Anwar BhattiRISE, Sweden, Muhammad Hamad AlizaiLUMS, Pakistan, Junaid Haroon SiddiquiLahore University of Management Sciences, Luca MottolaPolitecnico di Milano, Italy and RI.Se SICS, Sweden