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LCTES 2019
Sat 22 - Fri 28 June 2019 Phoenix, Arizona, United States
co-located with PLDI 2019
Sun 23 Jun 2019 12:05 - 12:20 at 105A - Session 2: Architecture and Compilers Chair(s): Na Meng

Wireless communication standards such as Long Term Evolution (LTE) are rapidly changing to support the high data rate of wireless devices. The physical layer baseband processing has strict real-time deadlines, especially in the next-generation applications enabled by the 5G standard. Existing base station transceivers utilize customized Digital Signal Processing (DSP) cores or fixed-function hardware accelerators for physical layer baseband processing. However, these approaches incur significant non-recurring engineering costs and are inflexible to newer standards or updates. Software programmable processors offer more adaptability. However, it is challenging to sustain guaranteed worst-case latency and throughput at reasonably low-power on shared-memory many-core architectures featuring inherently unpredictable design choices, such as caches and network-on-chip.

We propose SPECTRUM, a predictable software defined many-core architecture that exploits the massive parallelism of the LTE baseband processing. The focus is on designing a scalable lightweight hardware that can be programmed and defined by sophisticated software mechanisms. SPECTRUM employs hundreds of lightweight in-order cores augmented with custom instructions that provide predictable timing, a purely software-scheduled on-chip network that orchestrates the communication to avoid any contention and per-core software controlled scratchpad memory with deterministic access latency. Compared to a many-core architecture like Skylake-SP (average power 215W) that drops 14% packets at high traffic load, 256-core SPECTRUM by definition has zero packet drop rate at significantly lower average power of 24W. SPECTRUM consumes 2.11x lower power than C66x DSP cores+accelerator platform in baseband processing. SPECTRUM is also well-positioned to support future 5G workloads.

Sun 23 Jun

Displayed time zone: Tijuana, Baja California change

11:20 - 12:35
Session 2: Architecture and CompilersLCTES 2019 at 105A
Chair(s): Na Meng Virginia Tech
11:20
15m
Full-paper
From Java to Real-Time Java: A Model-Driven Methodology with Automated Toolchain (Invited)
LCTES 2019
Wanli Chang University of York, Shuai Zhao University of York, Ran Wei University of York, Andy Wellings University of York, Alan Burns University of York
11:35
15m
Full-paper
The Betrayal of Constant Power × Time: Finding the Missing Joules of Transiently-Powered Computers
LCTES 2019
Saad Ahmed LUMS, Pakistan, Abu Bakar Northwestern University, US, Naveed Anwar Bhatti RISE, Sweden, Muhammad Hamad Alizai LUMS, Pakistan, Junaid Haroon Siddiqui , Luca Mottola Politecnico di Milano, Italy and RI.Se SICS, Sweden
11:50
15m
Full-paper
WCET-Aware Hyper-Block Construction for Clustered VLIW Processors
LCTES 2019
Xuesong Su UNSW Sydney, Hui Wu University of New South Wales, Australia, Jingling Xue UNSW Sydney
12:05
15m
Full-paper
SPECTRUM: A Software Defined Predictable Many-core Architecture for LTE Baseband Processing
LCTES 2019
Vanchinathan Venkataramani National University of Singapore, Aditi Kulkarni National University of Singapore, Tulika Mitra National University of Singapore, Singapore, Li-Shiuan Peh National University of Singapore
12:20
15m
Full-paper
Efficient Intermittent Computing with Differential Checkpointing
LCTES 2019
Saad Ahmed LUMS, Pakistan, Naveed Anwar Bhatti RISE, Sweden, Muhammad Hamad Alizai LUMS, Pakistan, Junaid Haroon Siddiqui , Luca Mottola Politecnico di Milano, Italy and RI.Se SICS, Sweden