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LCTES 2019
Sat 22 - Fri 28 June 2019 Phoenix, Arizona, United States
co-located with PLDI 2019
Sun 23 Jun 2019 12:05 - 12:20 at 105A - Session 2: Architecture and Compilers Chair(s): Na Meng

Wireless communication standards such as Long Term Evolution (LTE) are rapidly changing to support the high data rate of wireless devices. The physical layer baseband processing has strict real-time deadlines, especially in the next-generation applications enabled by the 5G standard. Existing base station transceivers utilize customized Digital Signal Processing (DSP) cores or fixed-function hardware accelerators for physical layer baseband processing. However, these approaches incur significant non-recurring engineering costs and are inflexible to newer standards or updates. Software programmable processors offer more adaptability. However, it is challenging to sustain guaranteed worst-case latency and throughput at reasonably low-power on shared-memory many-core architectures featuring inherently unpredictable design choices, such as caches and network-on-chip.

We propose SPECTRUM, a predictable software defined many-core architecture that exploits the massive parallelism of the LTE baseband processing. The focus is on designing a scalable lightweight hardware that can be programmed and defined by sophisticated software mechanisms. SPECTRUM employs hundreds of lightweight in-order cores augmented with custom instructions that provide predictable timing, a purely software-scheduled on-chip network that orchestrates the communication to avoid any contention and per-core software controlled scratchpad memory with deterministic access latency. Compared to a many-core architecture like Skylake-SP (average power 215W) that drops 14% packets at high traffic load, 256-core SPECTRUM by definition has zero packet drop rate at significantly lower average power of 24W. SPECTRUM consumes 2.11x lower power than C66x DSP cores+accelerator platform in baseband processing. SPECTRUM is also well-positioned to support future 5G workloads.

Sun 23 Jun

LCTES-2019-papers
11:20 - 12:35: LCTES 2019 - Session 2: Architecture and Compilers at 105A
Chair(s): Na MengVirginia Tech
LCTES-2019-papers11:20 - 11:35
Full-paper
Wanli ChangUniversity of York, Shuai ZhaoUniversity of York, Ran WeiUniversity of York, Andy WellingsUniversity of York, Alan BurnsUniversity of York
LCTES-2019-papers11:35 - 11:50
Full-paper
Saad AhmedLUMS, Pakistan, Abu BakarNorthwestern University, US, Naveed Anwar BhattiRISE, Sweden, Muhammad Hamad AlizaiLUMS, Pakistan, Junaid Haroon SiddiquiLahore University of Management Sciences, Luca MottolaPolitecnico di Milano, Italy and RI.Se SICS, Sweden
LCTES-2019-papers11:50 - 12:05
Full-paper
Xuesong SuUNSW Sydney, Hui WuUniversity of New South Wales, Australia, Jingling XueUNSW Sydney
LCTES-2019-papers12:05 - 12:20
Full-paper
Vanchinathan VenkataramaniNational University of Singapore, Aditi KulkarniNational University of Singapore, Tulika MitraNational University of Singapore, Singapore, Li-Shiuan PehNational University of Singapore
LCTES-2019-papers12:20 - 12:35
Full-paper
Saad AhmedLUMS, Pakistan, Naveed Anwar BhattiRISE, Sweden, Muhammad Hamad AlizaiLUMS, Pakistan, Junaid Haroon SiddiquiLahore University of Management Sciences, Luca MottolaPolitecnico di Milano, Italy and RI.Se SICS, Sweden