Invited Talk - "End-to-End Verification of Intelligent Cyber-Physical Systems: Progress and Challenges"
Self-driving cars and other autonomous cyber-physical systems (CPS) infuse machine and reinforcement learning into safety-critical decision making processes. Recent work on formal methods for reinforcement learning agents demonstrates the potential of verification to increase the safety and robustness of intelligent control algorithms. Similarly, recent work applying SMT solvers to trained neural networks demonstrates how verification can be used to certify robustness of vision systems to adversarial examples. Despite these advances in safe control and safe perception, obtaining end-to-end safety guarantees that unify safe perception with safe control in under-modeled environments remains a largely unsolved problem. This talk will review recent work on safe AI for cyber-physical systems and illustrate several CPS-inspired challenges for the AI verification community.
Sat 6 AprDisplayed time zone: Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna change
09:00 - 10:30 | |||
09:00 30mTalk | Welcome to InterAVT 2019 InterAVT Stylianos Basagiannis United Technologies Research centre, Goetz Botterweck Lero - The Irish Software Research Centre and University of Limerick, Anila Mjeda Lero - The Irish Software Research Centre and University of Limerick | ||
09:30 30mTalk | Invited Talk - "End-to-End Verification of Intelligent Cyber-Physical Systems: Progress and Challenges" InterAVT Nathan Fulton MIT-IBM Watson AI Lab | ||
10:00 10mTalk | Cross Programming Language Taint Analysis for the IoT Ecosystem InterAVT Pietro Ferrara JuliaSoft SRL, Italy, Amit Kr Mandal Università Ca' Foscari, Venezia, Italy, Agostino Cortesi Università Ca' Foscari Venezia, Fausto Spoto U. Verona | ||
10:10 10mTalk | FVL: Formal Verification in the Loop to Enhance Verification of Safety-Critical Cyber-Physical Systems InterAVT Cinzia Bernardeshi Univ. of Pisa, Andrea Domenici University of Pisa, Italy, Sergio Saponara University of Pisa, Italy | ||
10:20 10mTalk | Rigorous Design of FDIR Systems with BIP InterAVT |